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Variable Length Multi-Objective Whale Optimization for Trust Aware Data Gathering in Wireless Sensor Network

IEEE Access 2025年 13卷 32100-32121页

作者： Saad, Mohammed Ayad Jaafar, Rosmina Chellappan, Kalaivani Faculty of Engineering and Built Environment Department of Electrical Electronics and System Engineering Selangor Bangi43600 Malaysia Al-Kitab University Department of Medical Instrumentations Technique Engineering Kirkuk36001 Iraq Universitas Airlangga Biomedical Engineering Study Program Faculty of Science and Technology Surabaya60115 Indonesia

Efficient data collection in wireless sensor networks (WSNs) is crucial. While traditional approaches rely on stationary data sinks, the use of mobile sinks, like unmanned aerial vehicles (UAVs), has shown promise in enhancing data-gathering capabilities. However, existing methods often overlook the importance of trust, leaving the network susceptible to malicious or faulty nodes. To address this issue, we propose a novel trust-aware data-gathering algorithm, Variable Length Multi-Objective Whale Optimization Data Gathering (VLMOWO-DG). Our algorithm simultaneously optimizes energy consumption, delay, and trust while employing mobile sinks to collect data from sensor nodes. By considering trust as a key performance metric, we improve data reliability and security. The VLMOWO-DG algorithm introduces flexibility through variable-length solution representation and application-oriented operators, allowing for efficient exploration of the solution space. Simulation results demonstrate that our proposed algorithm significantly outperforms established benchmarks, NSGA-II and NSGA-III, in terms of domination and hypervolume. This leads to a remarkable improvement of 200% in data gathering performance. © 2015 The Authors.

关键词： Data collection

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Hybrid Beamforming for Wideband Terahertz Massive MIMO Communications with Low-Resolution Phase Shifters and True-Time-Delay

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IEEE Transactions on Wireless Communications 2024年第7期23卷 8000-8012页

作者： Chang, Ping-Hsiang Chiueh, Tzi-Dar Graduate Institute of Electronics Engineering National Taiwan University Taipei10617 Taiwan Mediatek Inc. Hsinchu30078 Taiwan National Taiwan University Department of Electrical Engineering The Graduate School of Advanced Technology Taipei10617 Taiwan

Hybrid beamforming has attracted considerable interest in the development of next-generation wireless communications operating in the terahertz (THz) band. The short wavelength of THz wave has enabled thousands of antennas to be tightly packed inside a small area to provide sharp and accurate beamforming. Unfortunately, the beam squint effect, which changes the direction of beams as the frequency shifts, can only be circumvented by introducing true-time-delay (TTD) lines in the hybrid beamformers. However, most previous works neglected the resolution limitation of the precoding hardware and assumed phase shifters (PSs) and TTDs with infinite resolution. This paper proposes two quantized hybrid beamforming algorithms for the PS-only hybrid architecture and the TTD-assisted hybrid beamformer. We use a gradient descent approach with differentiable soft quantization techniques to overcome quantizer discontinuity. The RF precoder and the baseband precoder are alternately updated to maximize the similarity with the optimal precoder. Simulation results demonstrate the effectiveness of the proposed algorithms. The proposed 3-bit PS-only beamformer can achieve near-optimal performance and outperform other low-resolution precoding methods in a moderate squint scenario. The proposed low-resolution TTD-assisted architecture can effectively compensate severe squint effect and achieves near-optimal performance. © 2002-2012 IEEE.

关键词： Beamforming

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Detection of PCB Socket Defects: A Comparative Analysis of Transfer Learning, Semantic Segmentation and Feature Optimization Techniques

Detection of PCB Socket Defects: A Comparative Analysis of T...

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2024 International Conference on Intelligent Communication, Sensing and Electromagnetics, ICSE 2024

作者： Celik, Salih Senol, Yavuz Graduate School of Natural and Applied Sciences Dokuz Eylül University Department of Electrical and Electronics Engineering Izmir Turkey Engineering Dokuz Eylül University Department of Electrical and Electronics Engineering Izmir Turkey

ISBN: (纸本)9798350354935

The reliability and functionality of electronic components are critically important for efficiency in industrial production. As one of the fundamental components, printed circuit boards (PCBs) playa crucial role in the operational performance of electronic devices. Any defects in PCBs can lead to operational disruptions and increased costs. Specifically, sockets where sensors are connected are among the most susceptible areas for defects, and accurate and effective detection of these defects is vital for maintaining product quality and operational efficiency. Traditional defect detection methods typically rely on manual inspections, which are time-consuming and prone to human error, limiting their reliability. Advances in machine learning and image processing offer promising alternatives for automated defect detection. In this study, the performances of transfer learning (Googlenet) and semantic segmentation (U-Net) were compared for the classification of socket defects on a PCB. The dataset used in the study was specifically created for this research. The performances of three different models Googlenet, Googlenet+Relieff, and U-Net were evaluated. The Googlenet+Relieff model was identified as the most successful with an impressive accuracy rate of 98.6% and a classification time of 0.274 seconds. This high success rate demonstrates the effectiveness of combining feature selection algorithms with transfer learning. The results indicate that transfer learning has significant potential for improving industrial quality control processes. © 2024 IEEE.

关键词： Semantic Segmentation

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A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array

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IEEE Microwave and Wireless Technology Letters 2024年第6期34卷 679-682页

作者： You, Ying-Han Chen, Sih-Ying Lin, Pin-Yu Chien, Jun-Chau National Taiwan University Graduate Institute of Electronics Engineering Taipei10617 Taiwan University of California at Berkeley Department of Electrical Engineering and Computer Sciences BerkeleyCA94720 United States

This letter presents a 60-GHz analog phase-locked loop (PLL) incorporating a half-wavelength standing-wave oscillator (SWO) as part of the clock distribution network in a sub-THz 2-D phased-array transceiver. The frequency is selected as one-fourth of the target carrier frequency to comply with the 625-μ m half- wavelength element spacing requirement while facilitating array scaling. The PLL features a sampler-based phase detector (PD) and retiming flip-flop at the divider chain output to ensure minimal noise injection. Fabricated in TSMC 28-nm CMOS, the measurement results show an integrated jitter of 87.5 fsec from 1 kHz to 100 MHz. Consuming 31.35 mW of power, the presented PLL achieves a figure-of-merit of -270 dB. © 2023 IEEE.

关键词： Phase locked loops

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Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models 25

Physically Aware Wavelength-Routed Optical NoC Design for Cu...

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30th Asia and South Pacific Design Automation Conference, ASP-DAC 2025

作者： Kao, Wei-Yao Lin, Tai-Jung Chang, Yao-Wen Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Graduate School of Advanced Technology National Taiwan University Taipei Taiwan Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)9798400706356

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for system-on-chip designs. Recent work in the WRONoC topology designs mainly utilizes crossing switching elements (CSEs) as switching mechanisms on predefined templates. However, using CSEs incurs more microring resonator (MRR) usage and waveguide crossings than parallel switching elements (PSEs), and their predefined templates constrain the solution spaces. To remedy these disadvantages, we propose a fully automated topology design flow that utilizes PSE structures to reduce MRR usage and waveguide crossings. Our add-drop filter sequence model expands the solution space and leverages the advantage of the crossing-free PSE structure. Our fixed-node crossing-aware edge routing effectively minimizes the waveguide crossings, and our A∗-search preserves the admissibility property and guarantees an optimal routing solution. Besides, our design flow thoroughly considers the physical layout information. Experimental results show that our design substantially outperforms state-of-the-art works on customized designs. © 2025 Copyright is held by the owner/author(s). Publication rights licensed to ACM.

关键词： Network-on-chip

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A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with One-Tap DFE and Time-Interpolation

A 14.7-20-Gb/s Reference-Less Baud-Rate CDR Circuit with One...

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2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024

作者： Chou, Po-Yuan Liu, Shen-Iuan Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei Taiwan

ISBN: (纸本)9798350360349

A 14.7-20-Gb/s reference-less baud-rate clock and data recovery (CDR) circuit with a one-tap decision feedback equalizer is presented. The asymmetrical phase characteristic of the modified Mueller-Muller phase detector (MMPD) is analyzed and utilized for frequency acquisition. The frequency capture range can cover the entire frequency range of the voltage-controlled oscillator. The number of high-speed comparators in the modified MMPD is reduced by using the time-interpolated latch. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1219 mm2. For a 20 Gb/s PRBS of 27-1, the power is 53.4mW and its energy efficiency is 2.66pJ/b. © 2024 IEEE.

关键词： Clock and data recovery circuits (CDR circuits)

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A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative DFE and Reused Comparators

A 48-Gb/s Baud-Rate PAM-4 Receiver With One-Tap Speculative ...

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2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024

作者： Huang, Yuan-Pang Liu, Shen-Iuan Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei Taiwan

ISBN: (纸本)9798350360349

A 48-Gb/s quarter-rate four-level pulse amplitude modulation receiver with a one-tap speculative decision-feedback equalizer and a baud-rate clock and data recovery circuit is presented. By using the time-based technique, 8 comparators and 4 time-based latches are used. The offset voltages of these comparators and the time-based latches are calibrated in the foreground. This chip is fabricated in a 40-nm CMOS process and the active area is 0.1232mm2. The power consumption is 85.08mW and the calculated energy efficiency is 1.77pJ/b. © 2024 IEEE.

关键词： Pulse amplitude modulation

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A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwith One-Tap DFE

A 20-Gb/s Jitter-Tolerance-Enhanced Baud-Rate CDR Circuitwit...

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2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024

作者： Peng, Hsi-Kai Liu, Shen-Iuan Graduate Institute of Electronics Engineering National Taiwan University Department of Electrical Engineering Taipei Taiwan

ISBN: (纸本)9798350360349

A 20Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision-feedback equalizer (DFE) is presented. To widen the timing region of the clock, a foreground calibration circuit is presented to calibrate the threshold voltage of the comparator. It enhances the jitter tolerance (JTOL). This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.103mm2. The total power is 47.6mW and the calculated power efficiency is 2.38pJ/b at 20Gb/s. The measured high-frequency JTOL is larger than 0.2UIPP and the settling time of this calibration circuit is less than 12.7μs.. © 2024 IEEE.

关键词： Feedback

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A 185-μW, ±2.5-ppm -40°C-80°C Analog TCXO With A Differential-Pair-Based Polynomial Temperature Compensation Technique

A 185-μW, ±2.5-ppm -40°C-80°C Analog TCXO With A Differe...

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2024 IEEE Asian Solid-State Circuits Conference, A-SSCC 2024

作者： Fang, Chia-Hsi Lin, Chun-Yu Yang, Shuan Tsou, Shan-Chih Wen, Shon-Hang Chen, Kuan-Dar Lin, Tsung-Hsien Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University Taipei Taiwan MediaTek Hsinchu Taiwan

Crystal oscillators (XO) are widely used in electronic systems, providing low-jitter and temperature-stable reference clock signals. The inherent frequency accuracy of XO is good of ± 10ppm within a range of -40 ... 详细信息

ISBN: (纸本)9798350376326

关键词： Crystal oscillators

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Robust event-triggered data-driven control subject to control constraints

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Soft Computing 2024年第23期28卷 13083-13096页

作者： Echreshavi, Zeinab Farbood, Mohsen Shasadeghi, Mokhtar Mobayen, Saleh Department of Electrical and Electronics Engineering Shiraz University of Technology Shiraz Iran Department of Electrical Engineering University of Zanjan Zanjan45371-38791 Iran Graduate School of Intelligent Data Science National Yunlin University of Science and Technology Yunlin Douliu640301 Taiwan

This paper concerns with the problem of robust event-triggered data-driven control (DDC) considering control input and rate control constraints, simultaneously for discrete-time multi-input multi-output (MIMO) linear systems such that only the noisy data are measurable. Firstly, the data-dependent representation of the closed-loop system controlled by an event-triggered-based feedback control law is obtained. More precisely, to reduce the unnecessary communication resources, the control input updates and consequently, improve the system performance, event-triggered mechanism is utilized to design a stabilizing controller. Under a decreasing triggering threshold and a quadratic Lyapunov function, the ultimate boundedness stability (UBS) of the closed-loop system is ensured and the bounded region is expressed. Sufficient conditions for the UBS of the system are derived in terms of data-dependent linear matrix inequalities (LIMs). To meet the practical problems such as inherent limitations of the practical systems and to maximize the life-time of the actuators, the control input and rate control constraints are considered, simultaneously in the design procedure. In this scenario, the sufficient conditions are also obtained based on data-dependent LMIs. Finally, to demonstrate the effectiveness of the proposed control method, the recommended robust constrained event-triggered DDC is implemented to a numerical example and the simulation results demonstrate the validity of the proposed control approach. Moreover, a table is presented to compare the practical metrics such as robustness, necessities of the model plant identification, computational burden and control input constraints to verify the superiorities of the proposed method despite the existing results. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2024.

关键词： MIMO systems

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