The Human-Centered Internet of Things(HC-IoT)is fast becoming a hotbed of security and privacy *** users can establish a common session key through a trusted server over an open communication channel using a three-par...
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The Human-Centered Internet of Things(HC-IoT)is fast becoming a hotbed of security and privacy *** users can establish a common session key through a trusted server over an open communication channel using a three-party authenticated key *** of the early authenticated key agreement systems relied on pairing,hashing,or modular exponentiation processes that are computationally intensive and *** order to address this problem,this paper offers a new three-party authenticated key agreement technique based on fractional chaotic *** new scheme uses fractional chaotic maps and supports the dynamic sensing of HC-IoT devices in the network architecture without a password *** projected security scheme utilized a hash function,which works well for the resource-limited HC-IoT *** results show that our new technique is resistant to password guessing attacks since it does not use a ***,our approach provides users with comprehensive privacy protection,ensuring that a user forgery attack causes no ***,our new technique offers better security features than the techniques currently available in the literature.
The wavelength-routed optical network-on-chip (WRONoC) emerges as a promising solution for multi-core system communication, providing high-bandwidth, high-speed, and low-power transmission. As the number of cores in a...
The wavelength-routed optical network-on-chip (WRONoC) emerges as a promising solution for multi-core system communication, providing high-bandwidth, high-speed, and low-power transmission. As the number of cores in a WRONoC increases, however, some WRONoC topologies could be infeasible with bandwidth and crosstalk constraints if bit-level parallelism is not considered during topology generation. Previous work optimized the parallelism only for the radius selection of microring resonators but not for topology generation. To remedy this drawback, we present a parallelism-aware WRONoC topology generation flow. The proposed flow guarantees to generate a parallelism-optimal topology for full connectivity; and a parallelism-optimal topology for customized connectivity if the netlist meets certain conditions. Compared with the state-of-the-art methods, experimental results show a 67.5% improvement in parallelism.
Pre-trained language models based on deep learning have achieved significant improvements in natural language processing. Many studies have been published to investigate the knowledge in language models. In this paper...
Pre-trained language models based on deep learning have achieved significant improvements in natural language processing. Many studies have been published to investigate the knowledge in language models. In this paper, we investigate the extraction of subjective information from generative artificial intelligence models, show that the extraction of subjective information from language models is possible, and discuss superior extraction methods.
Convolutional neural networks (CNNs) are leveraged in many applications, such as image classification and natural language processing (NLP) tasks. However, the hardware implementation of CNNs not only occupies a consi...
Convolutional neural networks (CNNs) are leveraged in many applications, such as image classification and natural language processing (NLP) tasks. However, the hardware implementation of CNNs not only occupies a considerable amount of memory space but also incurs high computational demands, which can lead to significant energy cost for data transfer. Therefore, an emerging computing-in-memory (CIM)- based architecture has been proposed to alleviate the energy bottleneck of CNNs. Various model compression methods have recently been studied to enhance energy efficiency of the CIM-based accelerator, including quantization and pruning. However, these works are separately discussed with the static inference scenario. In this paper, the proposed DE-C3 can dynamically and jointly design the compression strategy. Besides, it adopts trainable energy-aware thresholds for both quantization and pruning scenarios. Experimental results based on the CIFAR-10 dataset show that our DE-C3 achieves up to 3.4× the energy reduction compared to state-of-the-art works.
MOS capacitor is widely used in modern semiconductor industry, especially for memory usage. In this work, transient currents read at millisecond-scale of MOS with ultra-thin oxide in voltage-switching programs were st...
MOS capacitor is widely used in modern semiconductor industry, especially for memory usage. In this work, transient currents read at millisecond-scale of MOS with ultra-thin oxide in voltage-switching programs were studied by experiment and simulation. Read current was observed to be saturated for a large enough write voltage, and was found to be maximal at appropriate oxide thickness. Even when too many inversion electrons were stored initially for write voltage greater than saturation voltage, electron density would decay rapidly and a number of holes would drift in for recombination within the first 1 ms due to the too small band bending. As a result, there would be a saturated value of inversion charges stored at millisecond time scale. The transient behavior studied in this work is fundamental and should be considered in the design of dynamic memory device.
Human-object interaction (HOI) detection is the task of predicting the visual relationships between humans and their surroundings in images and videos by locating and inferring the interactions between human-object pa...
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Perovskite solar cell (PSC) shows an outstanding performance growth in the last decade. The high-performing PSC currently is still on a laboratory scale and utilizes a noble metal for its counter electrode. The use of...
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Topological quantum error correction (TQEC) is a promising method for fault-tolerant quantum circuits. A TQEC circuit can be visualized as the defect movement along the time axis and modeled as a 3D space-time volume ...
Topological quantum error correction (TQEC) is a promising method for fault-tolerant quantum circuits. A TQEC circuit can be visualized as the defect movement along the time axis and modeled as a 3D space-time volume to estimate the required resource. A quantum algorithm must minimize the space-time volume for a feasible physical qubit number and computational time, especially for large-scale designs. Previous work presents quadratic-time simultaneous primal and dual bridge compression for a TQEC circuit, which is infeasible for large-scale problems. This paper presents an efficient divide-and-conquer approach to primal and dual bridge compression, which can support different code distances between qubits. Compared with the previous work, experimental results show that our algorithm is effective and efficient even for large-scale problems.
Edge-cloud collaborative systems are becoming essential for neural networks in edge applications. However, while applying pruning on the edge model is a typical process, previous works have simply removed the networks...
Edge-cloud collaborative systems are becoming essential for neural networks in edge applications. However, while applying pruning on the edge model is a typical process, previous works have simply removed the networks' sparsity with a global strategy, neglecting the filters' traits, environmental constraints, and edge-cloud joint optimization. This may lead to sub-optimal performance. In this paper, we propose a trainable pruning method considering system optimization. We introduce trainable gates to achieve filter-wise optimization regarding computation-aware and bandwidth-aware training to achieve a better performance. In addition, we adopt a performance predictor and a two-stage training strategy to estimate the optimal constraints-accuracy trade-off to the entire system. Finally, we validate the proposed method on the CIFAR-100 and the Tiny-ImageNet-200 dataset, and the results show that our approach significantly reduces the computation complexity and bandwidth requirement by approximately $ 75\%$ and $ 70\%$ compared to the prior work.
Two-dimensional directed self-assembly (2D-DSA) is an emerging lithography technology for advanced process nodes. We can determine the orientations of double posts to guide block copolymers to form feasible 2D guiding...
Two-dimensional directed self-assembly (2D-DSA) is an emerging lithography technology for advanced process nodes. We can determine the orientations of double posts to guide block copolymers to form feasible 2D guiding template patterns by the 2D-DSA process. This paper presents the first work to handle the 2D-DSA simultaneous placement and routing problem. We first propose a novel graph to model feasible guiding templates with a constant-time update scheme for each double-post assignment. Based on a graph model, we then present an algorithm for 2D-DSA simultaneous placement and routing, with a broadcast-based cost function for 2D-DSA cell placement and a graph-based scheme for DSA-compliant routing. Finally, we employ a strongly effective region property to minimize the cuts in the final layout. Experimental results show that our algorithm can efficiently generate a 2D-DSA placement and routing solution with high routability and a low cut number.
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