Dynamic Bayesian Networks(DBNs) provide a systematic framework for robust online monitoring of dynamic *** paper presents an approach for increasing the efficiency of online estimation by partitioning a system DBN int...
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Dynamic Bayesian Networks(DBNs) provide a systematic framework for robust online monitoring of dynamic *** paper presents an approach for increasing the efficiency of online estimation by partitioning a system DBN into a set of smaller factors,such that estimation algorithms can be applied to each factor *** factoring scheme is based on the analysis of structural observability of the dynamic *** establish the theoretical background for structural observability and derive an algorithm for generating the factors using structural observability *** present experimental results to demonstrate the effectiveness of our factoring approach for accurate estimation of system behavior.
software development and maintenance are highly distributed processes that involve a multitude of supporting tools and resources. Knowledge relevant to these resources is typically dispersed over a wide range of artif...
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software development and maintenance are highly distributed processes that involve a multitude of supporting tools and resources. Knowledge relevant to these resources is typically dispersed over a wide range of artifacts, representation formats, and abstraction levels. In order to stay competitive, organizations are often required to assess and provide evidence that their software meets the expected requirements. In our research, we focus on assessing non-functional quality requirements, specifically evolvability, through semantic modeling of relevant software artifacts. We introduce our SE-Advisor that supports the integration of knowledge resources typically found in software ecosystems by providing a unified ontological representation. We further illustrate how our SE-Advisor takes advantage of this unified representation to support the analysis and assessment of different types of quality attributes related to the evolvability of software ecosystems.
The purpose of this paper is to present a new size metric for business process *** metric aims to measure size of process from use case *** metric consists of four series to support four perspectives of business proce...
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The purpose of this paper is to present a new size metric for business process *** metric aims to measure size of process from use case *** metric consists of four series to support four perspectives of business process:functional,behavioral,informational and *** addition,the guidance for pointing to related use case elements is included in each *** this paper,each size of perspective which measured from the new metric can use for indicating the number of business process elements are represented by UML-activity *** the example of the metric is only one,it is possible to apply for another modeling method such as BPMN,Petri Net and EPC.
For the alarm flooding problem, a hierarchical alarm processing model is studied to filter, reduce and correlate alarms. In filtering, false alarms are eliminated with repository. In reduction, a reduction algorithm i...
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Design patterns are applied to solve the recurring software design problems,Unfortunately,choosing appropriate design patterns for the specific design problem is considered a difficult task.A search tool is,therefore,...
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Design patterns are applied to solve the recurring software design problems,Unfortunately,choosing appropriate design patterns for the specific design problem is considered a difficult task.A search tool is,therefore,needed to supports selection,However,the existing design pattern searching methodologies generally have problems on keywordsearch *** this paper,we proposed an initial model to solve the problem by using Case-Based Reasoning(CBR) and Formal Concept Analysis(FCA).For the proposed model,a case base is created to represent design *** is used to be case organization that analyze case base for obtain knowledge embedded,The knowledge can suggest suitable indexes to use for new *** method is beneficial for learning index,This paper discusses the basis theoretical of representation and retrieval design patterns for this inprogress research,along with some preliminary result.
software developers currently find design patterns through search tools for solving software design problem. However, these search tools still have keyword-search problem. In this paper, we introduce the elementary id...
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ISBN:
(纸本)9781424452446
software developers currently find design patterns through search tools for solving software design problem. However, these search tools still have keyword-search problem. In this paper, we introduce the elementary idea to improve the design pattern retrieval tool. We propose the combination of case based reasoning (CBR) and formal concept analysis (FCA). Because of CBR lead to the smart solution and FCA provides flexible way to maintain indexing in the case base.
Threats to information security for healthcare information system increased tremendously. There are various factors contribute to information security threats, many researchers focused only to certain factors which in...
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ISBN:
(纸本)9781424451012
Threats to information security for healthcare information system increased tremendously. There are various factors contribute to information security threats, many researchers focused only to certain factors which interest them (e.g., virus attack). Certain factors which may be important remain unexplored. In addition, lack of tools and technologies directed to limited number of threats traced in healthcare system. Thus it introduces bias in threat analysis. This study explored the use of biological computational termed Genetic Algorithm (GAs) combined with Cox regression (CoRGA) in identifying a potential threat for healthcare system. The results show that variable described “misused of e-mail” is the major information security threats for healthcare system. Results were compared with manual analysis using the same data, and it is shows that GAs not just introducing new threats for healthcare system but it was similar with others threats proposed by previous researches.
The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical late...
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The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems....
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Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the hard disk drives (HDD). Recent trends show that the solid state drives (SSD) such as flash memori...
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Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the hard disk drives (HDD). Recent trends show that the solid state drives (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.
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