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On the Single Event Upset Susceptibility of 10-nm SRAM Devices to Ionizing Radiation

IEEE Transactions on Nuclear Science 2025年第5期72卷 1768-1778页

作者： Seifert, Norbert Lee, Soonyoung Dorlus, Wydglif Mohammed, Rony Neale, Adam Pieper, Nicholas Intel Corporation Logic Technology Development Q&R HillsboroOR97124 United States Vanderbilt University Department of Electrical and Computer Engineering NashvilleTN37235 United States

In this work, we report on the radiation-induced soft error susceptibilities of three static random-access memory (SRAM) cell types fabricated on a 10-nm technology to various types of ionizing radiation, including high-energy and thermal neutrons, high-energy protons, alpha-particles, beta radiation, and heavy ions. Our results highlight that: 1) high-energy neutron (HEn) upset rates continue to dominate the total soft error rate (SER) in terrestrial radiation environments and 2) SERs continue to benefit from technology scaling. Accelerated testing projections demonstrate a ∼20× reduction in bit-level SERs between 45- and 10-nm SRAM cells of the same type. Results obtained from a three-year real-time test campaign are discussed and compared to accelerated testing projections and previous real-time testing results published by this team. Interestingly, the 10-nm real-time testing results show a consistent underestimation compared to projections obtained from accelerated beam testing. It is speculated that the scattering and absorption of HEns in the real-time testing setup are the main reasons for the observed discrepancy. Finally, single event upset (SEU) data are compared with selected space-weather databases, specifically gamma ray bursts (GRBs), ground level enhancements (GLEs), and solar energetic proton (SEP) events collected by the Geostationary Operational Environmental Satellites (GOES). No clear correlation is observed. © 1963-2012 IEEE.

关键词： Gamma rays

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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of

Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the IDS-vs.-VGS input-transfer characteristics. Subsequently, CMOS inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay (tpHL), falling time (tf), low-to-high propagation delay (tpLH), rising time (tr), overshoot voltage (Vov), and undershoot voltage (Vund). Based on the results, we suggest which CFET structure is more suitable for device scaling. © 1982-2012 IEEE.

关键词： CMOS integrated circuits

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A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 logic technology

IEEE Solid-State Circuits Letters

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IEEE Solid-State Circuits Letters 2025年

作者： Bhatt, Kedar Hutchins, Stafford Sanne, Atresh Hasan, Mohammad M. Chen, Zhanping Kulkarni, Jaydeep P. Intel Corporation Department of Logic Technology Development AustinTX78746 United States Intel Corporation Department of Logic Technology Development HillsboroOR97124 United States The University of Texas at Austin Electrical and Computer Engineering Department AustinTX78712 United States

A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop Band Gap Reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62V with 8.7mV sigma, and an overvoltage trip point of 1.22V with 12mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of 2μs, and brown-out detection of © 2018 IEEE.

关键词： Phase comparators

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A 5-V-Program 1-V-Sense Anti-Fuse technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

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IEEE Solid-State Circuits Letters 2021年 4卷 2-5页

作者： Kulkarni, Sarvesh H. Ikram, Umaira Bhatt, Kedar Chao, Yu-Lin Chang, Yao-Feng Jenkins, Ian Murari, Venkatesh Thambithurai, David Hasan, Mohammad Li, Jiabo Paulson, Leif R. Sell, Bernhard Bhattacharya, Uddalak Zhang, Ying Department of Logic Technology Development Intel Corporation HillsboroOR United States

A 11.56-kbit one-Time programmable secure array featuring Intel's first high-volume manufacturing (HVM) ready anti-fuse memory using the 22FFL process technology is reported. First, design and process technology are co-optimized to minimize the operating voltage, peripheral reliability stress, and area with dual gate-oxide 2-Transistor (2T) bit cells. Second, a best reported array density and 1-V sense endurance supported by a low-voltage dynamic scheme that meets on-demand read requirements at a yield of 99.99% are demonstrated. Third, this is the first demonstration of integrated power delivery for anti-fuse memory in FinFET technologies. With program voltage limited to 5 V, 2-stage 1.8-V charge pumps improve system area and integration. © 2018 IEEE.

关键词： FinFET

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The influence of Ar sputter cleaning on NiSi formation and NiSi junction leakage

The influence of Ar sputter cleaning on NiSi formation and N...

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6th International Conference on Semiconductor technology, ISTC2007

作者： Yang, Rui Peng Hu, Yuhui Bonfanti, Paolo Su, Na Nie, Jiaxiang Kang, Yun Logic Technology Development Department Semiconductor Manufacturing International Corp. Economic-Technological Development Area No. 18 Wenchang Road Beijing China

ISBN: (纸本)9889884445

A method to reduce junction leakage for 65 nm products was proposed. The study focused on the impact of Ar sputter cleaning (ASC) on Nickel silicide spiking and junction leakage. It was found by TEM that spiking decrease in PMOS area by eliminating ASC before Ni deposition. As a result, junction leakage was improved. Decreasing Plasma and bias power did not have obvious improvement and spiking still existed. The supposed plasma damage model was not supported by AFM data that Si substrate roughness did not have difference between before and after ASC. Here proposed a new model.

关键词： Silicides

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Investigation of post CMP voids in narrow trenches of 65 nm technology node

Investigation of post CMP voids in narrow trenches of 65 nm ...

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7th International Conference on Semiconductor technology, ISTC 2008

作者： Ruipeng, Yang Jiaxiang, Nie Yun, Kang Weiye, He Na, Su Bonfanti, Paolo Yuhui, Hu Logic Technology Development Department Semiconductor Manufacturing International Corp. Beijing Economic-Technological Development Area No. 18 Wenchang Road China

ISBN: (纸本)9789881740816

Smaller size copper lines which are widely used in sub-65nm process suffer more serious void defects. Aiming at this problem we did some research about the void defects generated in narrow metal line after chemical mechanical polishing (CMP). SAS DOE(design of experiment) software was applied in this study and the result showed that the ECP current, seed thickness and anneal temperature strongly affected the void existence. We did further research of these key factors, analyzed the mechanism and gave new scheme that can improve the copper void condition at a low risk.

关键词： Copper

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

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IEEE International Test Conference, ITC 2005

作者： Gill, Balkaran S. Papachristou, Chris Wolff, Francis G. Seifert, Norbert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH Logic Technology Development Q and R Intel Corporation Hillsboro OR

ISBN: (纸本)0780390393

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits. © 2005 IEEE.

关键词： CMOS integrated circuits

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Impact of the heat conductivity of the inert electrode on ReRAM performance and endurance 233

Impact of the heat conductivity of the inert electrode on Re...

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Symposium on Advanced CMOS-Compatible Semiconductor Devices 18 - 233rd ECS Meeting

作者： Al-Mamun, M. King, S.W. Meda, S.R. Orlowski, M. Bradley Department of Electric and Computer Engineering Virginia Tech. BlacksburgVA United States Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9781607688365

We report on the impact of the inert electrode on the endurance of ReRAM memory cells. The baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. We find consistently that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity. Specifically, Rh(150/Cr(94) (numbers represent the heat conductivity in units of W/(mK)) is not only superior to Pt(72)/Ti(20) but also to Rh(150)/Ti(20) device. We explain the impact of the heat conductivity of the inert electrode on the endurance by the deformation of the Cu filament due to Cu fluxes during the switching cycles. © The Electrochemical Society.

关键词： Thermal conductivity

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Mechanical stress field assisted charge de-trapping in carbon doped oxides

Mechanical stress field assisted charge de-trapping in carbo...

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作者： Alam, M.T. Maletto, K.E. Bielefeld, J. King, S.W. Haque, M.A. Department of Mechanical and Nuclear Engineering Pennsylvania State University University ParkPA16802 United States Logic Technology Development Intel Corporation HillsboroOR97124 United States

Leakage current and dielectric breakdown effects are conventionally studied under electrical fields alone, with little regard for mechanical stresses. In this letter, we demonstrate that mechanical stress can influence the reliability of dielectrics even at lower field strengths. We applied tensile stress (up to 8 MPa) to a 33% porous, 504 nm thick carbon doped oxide thin film and measured the leakage current at constant electrical fields (up to 2.5 MV/cm). The observed increase in leakage current at relatively low electric fields suggests that mechanical stress assists in trap/defect mediated conduction by reducing the energy barrier potential to de-trap charges in the dielectric. © 2015 Elsevier Ltd.

关键词： Electric breakdown

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Control of nano-porosity in plasma deposited low-k diffusion barrier and inter-layer dielectrics for nano-electronic applications

Control of nano-porosity in plasma deposited low-k diffusion...

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Materials Engineering and Sciences Division - Core Programming Topic at the 2011 AIChE Annual Meeting

作者： King, Sean Mays, Ebony Bielefeld, Jeff Liu, Ming Gidley, David Logic Technology Development Intel Corporation HillsboroOR United States Components Research Intel Corporation HillsboroOR United States Department of Physics University of Michigan Ann ArborMI United States

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