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A 5-V-Program 1-V-Sense Anti-Fuse technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

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IEEE Solid-State Circuits Letters 2021年 4卷 2-5页

作者： Kulkarni, Sarvesh H. Ikram, Umaira Bhatt, Kedar Chao, Yu-Lin Chang, Yao-Feng Jenkins, Ian Murari, Venkatesh Thambithurai, David Hasan, Mohammad Li, Jiabo Paulson, Leif R. Sell, Bernhard Bhattacharya, Uddalak Zhang, Ying Department of Logic Technology Development Intel Corporation HillsboroOR United States

A 11.56-kbit one-Time programmable secure array featuring Intel's first high-volume manufacturing (HVM) ready anti-fuse memory using the 22FFL process technology is reported. First, design and process technology are co-optimized to minimize the operating voltage, peripheral reliability stress, and area with dual gate-oxide 2-Transistor (2T) bit cells. Second, a best reported array density and 1-V sense endurance supported by a low-voltage dynamic scheme that meets on-demand read requirements at a yield of 99.99% are demonstrated. Third, this is the first demonstration of integrated power delivery for anti-fuse memory in FinFET technologies. With program voltage limited to 5 V, 2-stage 1.8-V charge pumps improve system area and integration. © 2018 IEEE.

关键词： FinFET

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Device Design Guidelines to Boost up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025年

作者： Lim, Jaehyuk Han, Donghwan Sung, Juho Yoon, Seokchan Kang, Sanghyun Kim, Gwon Baac, Hyoung Won Shin, Changhwan Sungkyunkwan University Department of Electrical and Computer Engineering Suwon16419 Korea Republic of Korea University School of Electrical Engineering Seoul02841 Korea Republic of Samsung Electronics Semiconductor Research and Development Center Logic Technology Development Team Hwaseong18448 Korea Republic of

Complementary Field-Effect Transistors (CFETs) have emerged as promising candidates for next-generation semiconductor devices. CFETs feature a structure with an NMOS (or PMOS) transistor at the bottom and a transistor of the opposite type at the top. CFETs can be classified into Fin-CFETs or GAA-CFETs based on their channel structure. In this study, we compare and analyze these two devices to determine which structure is more favorable for device scaling and which device exhibits better performance per unit area. For a reliable analysis, the threshold voltage was adjusted to be the same for all devices. Initially, to compare the DC performance, the on-state drive currents in both linear mode and saturation mode operations were extracted and compared from the IDS-vs.-VGS input-transfer characteristics. Subsequently, CMOS inverters were constructed to compare their AC performance. Six parameters were extracted and compared: high-to-low propagation delay (tpHL), falling time (tf), low-to-high propagation delay (tpLH), rising time (tr), overshoot voltage (Vov), and undershoot voltage (Vund). Based on the results, we suggest which CFET structure is more suitable for device scaling. © 1982-2012 IEEE.

关键词： CMOS integrated circuits

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Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs

Performance Comparison of SRAM Designs Implemented with Sili...

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European Conference on Solid-State Device Research (ESSDERC)

作者： Po-Chih Chen Yi-Ting Wu Meng-Hsueh Chiang Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Logic Technology Development Intel Corporation Hillsboro Oregon United States

This study compares six-transistor (6T) static random access memory (SRAM) implemented with state-of-the-art bulk FinFETs and silicon-on-insulator (SOI) gate-all-around nanosheet transistors (NSFETs) for G40M16/T2 (2 nm) process node. Compared to the FinFET 6T SRAM whose pull-up (PU), pass-gate (PG), and pull-down (PD) transistor footprint (device layout width) ratio can only be either PU:PG:PD = 1:1:2 or 1:2:2, the PU:PG:PD of NSFET SRAM can be 1:α:2, where α can be any number between 1 and 2 owing to the adjustable channel widths of PG transistors . The optimal read and write static noise margin (RSNM and WSNM) design is PU:PG:PD = 1:1.458:2, where the RSNM = WSNM = 171 mV, which is 14% and 51% higher than the minimum RSNM and WSNM values of 1:1:2 and 1:2:2 FinFET SRAMs respectively. Moreover, because the entire device above the SOI substrate of the SOI NSFET can conduct current, its drive current is 109% higher than that of bulk FinFET, in which the part of the device above the silicon substrate forms a punch-through stopper, which does not contribute to the conductive current. In addition, the read/write access time of NSFET SRAM is 49%/7% faster than that of the bulk FinFET SRAM under a 1:2:2 design owing to the higher drive current.

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Omni 3D: BEOL-Compatible 3D logic with Omnipresent Power, Signal, and Clock

arXiv

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arXiv 2024年

作者： Choi, Suhyeong Gilardi, Carlo Gutwin, Paul Radway, Robert M. Srimani, Tathagata Mitra, Subhasish The Department of Electrical Engineering Stanford University Korea Republic of Logic Technology Development Intel Corporation United States The Department of Electrical and Computer Engineering Carnegie Mellon University United States The Department of Electrical Engineering The Department of Computer Science Stanford University United States

This paper presents Omni 3D - a 3D-stacked device architecture that is naturally enabled by back-end-of-line (BEOL)-compatible transistors. Omni 3D arbitrarily interleaves metal layers for both signal/power with FETs in 3D (i.e., nFETs and pFETs are stacked in 3D). Thus, signal/power routing layers have fine-grained, all-sided access to the FET active regions maximizing 3D standard cell design flexibility. This is in sharp contrast to approaches such as back-side power delivery networks (BSPDNs), complementary FETs (CFETs), and stacked FETs. Importantly, the routing flexibility of Omni 3D is enabled by double-side routing and an interleaved metal (IM) layer for inter- and intra-cell routing, respectively. In this work, we explore Omni 3D variants (e.g., both with and without the IM layer) and optimize these variants using a virtual-source BEOL-FET compact model. We establish a physical design flow that efficiently utilizes the double-side routing in Omni 3D and perform a thorough design-technology-co-optimization (DTCO) of Omni 3D device architecture on several design points. From our design flow, we project 2.0× improvement in the energy-delay product and 1.5× reduction in area compared to the state-of-the-art CFETs with BSPDNs. © 2024, CC BY.

关键词： Integrated circuit design

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A Bandgap Diode-Based Voltage Band Detection Circuit With Fast Response Time and Low Vmin on Intel 4 logic technology

IEEE Solid-State Circuits Letters

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IEEE Solid-State Circuits Letters 2025年 8卷 157-160页

作者： Bhatt, Kedar Hutchins, Stafford Sanne, Atresh Hasan, Mohammad M. Chen, Zhanping Kulkarni, Jaydeep P. Intel Corporation Department of Logic Technology Development AustinTX78746 United States Intel Corporation Department of Logic Technology Development HillsboroOR97124 United States The University of Texas at Austin Electrical and Computer Engineering Department AustinTX78712 United States

A fast, accurate, single-rail voltage detection circuit (VDC) is presented. Low voltage operation is achieved by a variable gain Charge Pump (CP) followed by a Low-Dropout regulator (LDO). An Open-loop Band Gap Reference (BGREF), passed to a dynamic comparator, achieves an undervoltage trip point of 0.62V with 8.7mV sigma, and an overvoltage trip point of 1.22V with 12mV sigma, demonstrated on Intel 4 silicon prototype. The design operates without any filter cap, allowing a fast, power-on ramp of 2μs, and brown-out detection of © 2018 IEEE.

关键词： Phase comparators

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Density and atomic coordination dictate vibrational characteristics and thermal conductivity of amorphous silicon carbide

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Physical Review Materials 2022年第9期6卷 094601-094601页

作者： Sandip Thakur Connor Jaymes Dionne Pravin Karna Sean W. King William Lanford Han Li Shouvik Banerjee Devin Merrill Patrick E. Hopkins Ashutosh Giri Department of Mechanical Industrial and Systems Engineering University of Rhode Island Kingston Rhode Island 02881 USA Intel Corporation Logic Technology Development Hillsboro Oregon 97124 USA Physics Department University at Albany Albany New York 12206 USA Department of Mechanical and Aerospace Engineering University of Virginia Charlottesville Virginia 22904 USA Department of Materials Science and Engineering University of Virginia Charlottesville Virginia 22904 USA Department of Physics University of Virginia Charlottesville Virginia 22904 USA

Silicon carbide coatings and thin films are used for a wide array of applications ranging from thermal barrier coatings to microelectronics. In this paper, we report on the role of mass density and atomic coordination on the fundamental vibrational characteristics and thermal conductivity of amorphous silicon carbide systems through a combination of experiments and systematic atomistic simulations. We use time domain thermoreflectance to show that the thermal conductivity of hydrogenated amorphous silicon carbide can be increased twofold with ∼40% increase in the mass density. A simple description of thermal transport applicable to a range of amorphous solids where diffusion of thermal energy is predominantly driven by nonpropagating modes cannot fully describe our experimental measurements. Our molecular dynamics simulations in conjunction with our lattice dynamics calculations shed light on the intrinsic role of atomic coordination in dictating the contributions from both propagating and nonpropagating modes in amorphous silicon carbide structures. More specifically, we find that as the concentration of sp3 hybridized carbon atoms is increased by up to 10% with increasing mass densities, the contribution from propagons can be increased from ∼25% to ∼40%, after which further increments in the mass density and the sp3 fraction does not lead to higher contributions from propagons. In contrast, contributions from the nonpropagating modes increases monotonically with increasing mass density and sp3 hybridization. Our results pave a path forward to manipulate the thermal conductivity of amoprhous silicon carbide systems based on varying the atomic coordination.

关键词： Hardness Thermal conductivity Amorphous semiconductors

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X-ray photoemission investigation of the beryllium oxide band alignment with magnesium oxide and estimates for other insulating and conducting oxides 239

X-ray photoemission investigation of the beryllium oxide ban...

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239th ECS Meeting with the 18th International Meeting on Chemical Sensors, IMCS 2021

作者： Koh, D. Hudnall, T.W. Bielawski, C.W. Banerjee, S.K. Brockman, J. Kuhn, M. King, S.W. Microelectronics Research Center Department of Electrical and Computer Engineering University of Texas at Austin 10100 Burnet Road AustinTX78758 United States Department of Chemistry and Biochemistry Texas State University San MarcosTX78666 United States Ulsan44919 Korea Republic of Ulsan44919 Korea Republic of Ulsan44919 Korea Republic of Logic Technology Development Intel Corporation HillsboroOR97124 United States

ISBN: (纸本)9781607689164

Beryllium oxide (BeO) is a wurtzite structured, large bandgap (Eg > 8 eV) material of significant interest as an alloying agent and cladding dielectric in various oxide based optoelectronic devices. The success of such devices is highly reliant on bandgap and band alignment engineering to achieve sufficient charge carrier and optical confinement for device operation. In this regard, we have utilized x-ray photoemission spectroscopy (XPS) to determine the valence band offset (VBO) between atomic layer deposited (ALD) BeO and a (001) oriented magnesium oxide (MgO) substrate. The BeO VBO with MgO (001) was determined to be 0.1 ± 0.15 eV. Applying the rules of commutativity and transitivity for band alignment, we additionally predict the BeO VBO with other conductive oxides such as ZnO, Ga2O3, and InGaZnO4, to be 1.15 ± 0.3 eV, 0.3 ± 0.2 eV, and 0.9 ± 0.2 eV, respectively. © The Electrochemical Society

关键词： II-VI semiconductors

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Reliability Characterization for 12 V Application Using the 22FFL FinFET technology

Reliability Characterization for 12 V Application Using the ...

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Annual International Symposium on Reliability Physics

作者： C.-Y. Su M. Armstrong S. Chugh M. El-tanani H. Greve H. Li M. Maksud B. Orr C. Perini J. Palmer L. Paulson S. Ramey J. Waldemer Y. Yang D. Young Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A. Portland Technology Development Department Intel Corp. Hillsboro Oregon U.S.A. Device Development Group Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.

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Hydrogen effects on the thermal conductivity of delocalized vibrational modes in amorphous silicon nitride (a−SiNx:H)

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Physical Review Materials 2021年第3期5卷 035604-035604页

作者： Jeffrey L. Braun Sean W. King Eric R. Hoglund Mehrdad Abbasi Gharacheh Ethan A. Scott Ashutosh Giri John A. Tomko John T. Gaskins Ahmad Al-kukhun Gyanendra Bhattarai Michelle M. Paquette Georges Chollon Benjamin Willey G. Andrew Antonelli David W. Gidley Jinwoo Hwang James M. Howe Patrick E. Hopkins Department of Mechanical and Aerospace Engineering University of Virginia Charlottesville Virginia 22904 USA Intel Corporation Logic Technology Development 5200 NE Elam Young Parkway Hillsboro Oregon 97124 USA Department of Materials Science and Engineering University of Virginia Charlottesville Virginia 22904 USA Department of Materials Science and Engineering The Ohio State University Columbus Ohio 43210 USA Department of Mechanical Industrial and Systems Engineering University of Rhode Island Kingston Rhode Island 02881 USA Department of Physics and Astronomy University of Missouri-Kansas City Kansas City Missouri 64110 USA Laboratoire des Composites Thermostructuraux CNRS–SAFRAN Ceramics–CEA–University of Bordeaux 3 allee de La Boetie 33600 Pessac France Onto Innovation Portland Oregon 97202 USA Department of Physics University of Michigan Ann Arbor Michigan 48109 USA Department of Physics University of Virginia Charlottesville Virginia 22904 USA

Hydrogenated amorphous dielectric thin films are critical materials in a wide array of technologies. In this work, we present a thorough investigation of the thermal conductivity of hydrogenated amorphous silicon nitride (a−SiNx:H), a ubiquitously used material in which the stoichiometry plays a direct role in its functionality and application. In particular, through chemical, vibrational, and structural analysis in tandem with thermal conductivity measurements on chemically variant silicon nitride films, we show that hydrogen incorporation into silicon nitride disrupts the bonding among silicon and nitrogen atoms, and directly impacts the thermal conductivity, leading to as much as a factor of 2.5 variation in heat transfer. This variability, driven by the change in hydrogen content, is fundamentally related to the changes in the average atomic distances, as we experimentally measure with selected-area electron diffraction and computationally show with molecular dynamics simulations. This, combined with our evidence of chemical and spatial fluctuations on the order of average atomic pair distances, leads us to conclude that the vibrational heat transport in a−SiNx:H is primarily dominated by diffusonlike modes. The results presented in this work combined with our extensive review of prior reports on the thermal conductivity of a−SiNx:H films resolves discrepancies in decades of prior literature and facilitates a more universal understanding of the vibrational heat transport processes in hydrogenated amorphous silicon nitride.

关键词： Thermal conductivity Amorphous materials Molecular dynamics Thermoreflectance

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Impact of the heat conductivity of the inert electrode on ReRAM performance and endurance 233

Impact of the heat conductivity of the inert electrode on Re...

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Symposium on Advanced CMOS-Compatible Semiconductor Devices 18 - 233rd ECS Meeting

作者： Al-Mamun, M. King, S.W. Meda, S.R. Orlowski, M. Bradley Department of Electric and Computer Engineering Virginia Tech. BlacksburgVA United States Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9781607688365

We report on the impact of the inert electrode on the endurance of ReRAM memory cells. The baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. We find consistently that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity. Specifically, Rh(150/Cr(94) (numbers represent the heat conductivity in units of W/(mK)) is not only superior to Pt(72)/Ti(20) but also to Rh(150)/Ti(20) device. We explain the impact of the heat conductivity of the inert electrode on the endurance by the deformation of the Cu filament due to Cu fluxes during the switching cycles. © The Electrochemical Society.

关键词： Thermal conductivity

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