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检索条件"机构=Department of Logic Technology Development"

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HCI lifetime enhancement by double implanted S/D (DISD) of Nch MOSFET in 0.25 /spl mu/m CMOS technology

HCI lifetime enhancement by double implanted S/D (DISD) of N...

引用

IEEE International Workshop Integrated Reliability

作者： D. Wu S. Luning D.H. Ju N. Kepler Logic Technology Development Department Advanced Micro Devices Inc. Sunnyvale CA USA

The results of an intensive study of drain engineering work to improve the hot carrier injection (HCI) reliability of N-channel MOSFETs in 0.25 /spl mu/m CMOS technology are presented. While an As/P LDD structure improved HCI by sacrificing off-current, an alternative method of integrating phosphorus into the heavy dose As S/D junction delivers an equivalent HCI lifetime and an even lower off-current. Around one order of magnitude of HCI lifetime enhancement has been achieved with this P-doping of the S/D. Device simulations supported our approach.

关键词： Human computer interaction MOSFET circuits CMOS technology Oxidation Implants Application specific processors DH-HEMTs CMOS logic circuits logic devices Reliability engineering

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A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

A Method to Detect Bit Flips in a Soft-Error Resilient TCAM

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作者： Syafalni, Infall Sasao, Tsutomu Wen, Xiaoqing ASIC Development Group Logic Research Company Ltd. Fukuoka814-0001 Japan Department of Computer Science Meiji University Kawasaki214-8571 Japan Department of Creative Information Kyushu Institute of Technology Iizuka820-8502 Japan

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k. KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers. © 1982-2012 IEEE.

关键词： Static random access storage

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Atomic layer deposited hybrid organic-inorganic aluminates as potential low-κ dielectric materials

Atomic layer deposited hybrid organic-inorganic aluminates a...

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2015 MRS Spring Meeting

作者： Klepper, Karina B. Miikkulainen, Ville Nilsen, Ola Fjellvag, Helmer Liu, Ming Dutta, Dhanadeep Gidley, David Lanford, William Ross, Liza Li, Han King, Sean W. Department of Chemistry Center for Materials Science and Nanotechnology University of Oslo Oslo Norway Department of Physics University of Michigan Ann ArborMI United States Department of Physics University of Albany AlbanyNY United States Logic Technology Development Intel Corporation HillsboroOR United States

ISBN: (纸本)9781510826458

The material properties of atomic layer deposited hybrid organic-inorganic aluminate thin films have been evaluated for potential low dielectric constant (i.e. low-κ) applications. The hybrid aluminates were deposited using trimethyl aluminum and various linear and aromatic carboxylic acids. The observed electrical and mechanical properties for the hybrid aluminate films varied greatly depending on the selected organic acid with values ranging from 2.5 to 5.1 and Young's modulus ranging from 6 to 40 GPa. Leakage currents as low as 4 x 10-10 A/cm2 (at 2 MV/cm) were obtained for films grown using saturated linear carboxylic acids. These results suggest the potential of ALD hybrid aluminate thin films for low-κ dielectric applications. © 2015 Materials Research Society.

关键词： Thin films

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CMOS transistor reliability and performance impacted by gate microstructure

CMOS transistor reliability and performance impacted by gate...

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IEEE International Workshop Integrated Reliability

作者： B. Yu T.-J. King C. Hu D.-H. Ju N. Kepler Department of Electrical Engineering & Computer Sciences University of California Berkeley CA USA Technology Development Group Advanced Micro Devices Logic Technology Development Sunnyvale CA USA

This paper investigate the impact of CMOS (complementary metal-oxide-semiconductor) gate microstructure on the reliability and performance of deep-submicrometer CMOS transistors. The amorphous silicon (/spl alpha/-Si) gate provides better capability for suppression of boron penetration in p/sup +/ doped gate p-channel MOSFETs, but gate depletion in the /spl alpha/-Si gate is slightly more severe than that of the poly-Si gate. The gate-length-dependent gate-depletion effect, in which the difference in linear g/sub m/ between MOSFETs with two different gate microstructures shows a strong L/sub g/-dependence, is reported and interpreted by impurity diffusion along the grain boundary. A gate nitrogen implant as an effective method for suppression of the boron diffusion is also discussed with emphasis on the impact on both device reliability and performance.

关键词： Microstructure Boron CMOS technology MOSFETs CMOS process Integrated circuit technology Amorphous silicon Nitrogen Implants FETs

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Interfacial adhesion of thin-film patterned interconnect structures

Interfacial adhesion of thin-film patterned interconnect str...

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IEEE International Conference on Interconnect technology

作者： C. Litteken R. Dauskardt T. Scherban G. Xu J. Leu D. Gracias B. Sun Department of Materials Science and Engineering University of Stanford Stanford CA USA Logic Technology Development Intel Corporation Hillsboro OR USA Technology Development Intel Corporation Santa Clara CA USA

The interfacial adhesion of lithographically patterned thin film structures has been measured. Fracture mechanics techniques, modified for thin-film geometries, were employed to quantify the interfacial adhesion of patterned arrays containing low-k and Cu metal lines with varying channel length scales, aspect ratios and orientations. The results indicate that interfacial adhesion may be affected by the line structures and their orientation. In addition, the fracture resistance of debonded interface was dependent on the specific low-k material employed in the structure.

关键词： Adhesives Transistors Copper Residual stresses Polymer films Materials science and technology Energy dissipation Plastics Mechanical factors Dielectric thin films

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Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

Digital test circuit design and optimization for AC hot-carr...

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IEEE International Conference on Microelectronic Test Structures

作者： W. Jiang H. Le S.A. Kim J.E. Chung Y.-J. Wu P. Bendix J. Jensen R. Ardans S. Prasad A. Kapoor T.E. Kopley T. Dungan P. Marcoux EECS Department Massachusetts Institute of Technology Cambridge MA USA Research and Development LSI Logic Corporation Milpitas USA ICBD Technology Development Center Hewlett Packard Company Palo Alto USA

This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs are presented and additional new test circuit designs demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed.

关键词： Circuit testing Circuit synthesis Design optimization Hot carriers Inverters Ring oscillators logic testing Calibration Internal stresses Voltage-controlled oscillators

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A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs

A Blind Calibration Technique to Correct Memory Errors in Am...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Munkyo Seo Sopan Joshi Ian A. Young Department of Electrical and Computer Engineering University of California Santa Barbara CA USA Logic Technology Development Intel Corporation Hillsboro OR USA

The authors present a statistics-based blind calibration technique for nonlinear memory errors in amplifier-sharing pipelined ADCs. The proposed method is fully digital and simple to implement. It detects memory errors in normal operation without system suspension for calibration. No special calibration signal or analog circuitry is necessary. Algorithm description and simulation results are presented. The proposed technique improves the power efficiency of pipelined ADCs by enabling sharing of low-gain operational amplifiers.

关键词： Calibration Error correction Computer errors Circuits Pipelines Operational amplifiers logic arrays Capacitors CMOS technology Energy consumption

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Process integration of Cu metallization and ultra low k (k=2.2)

Process integration of Cu metallization and ultra low k (k=2...

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IEEE International Conference on Interconnect technology

作者： Chuan-cheng Cheng Wei-jen Hsia J. Pallinti S. Neumann J. Koh P. Li Mei Zhu M. Lu Hao Cui T. Fujimoto W. Catabay P. Wright Process Technology Department. Process R&D LSI Logic Corporation Santa Clara CA USA Process Module Development and Advance Research LSI Logic Corporation Gresham OR USA

The first process integration of Cu metallization and next generation CVD ultra low k (Trikon Orion ULK, k=2.2) is presented. The current process condition for a 130 nm node Cu/lowk (k=2.9) process is applied to Cu/ULK and found to be suitable without major modifications. The comparison of post CMP measurement (dishing, erosion, peeling, and scratch) show no significant variation between control (k=2.9) and ULK. The electrical data indicates the successful integration of Cu and ULK. The interconnect capacitance is expected to reduce 20% at 0.1 /spl mu/m technology node using the ULK film.

关键词： Metallization Etching Silicon carbide Chemistry Large scale integration logic Delay Dielectric materials Dielectric constant Inspection

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Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs

Performance Comparison of SRAM Designs Implemented with Sili...

引用

European Conference on Solid-State Device Research (ESSDERC)

作者： Po-Chih Chen Yi-Ting Wu Meng-Hsueh Chiang Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Logic Technology Development Intel Corporation Hillsboro Oregon United States

This study compares six-transistor (6T) static random access memory (SRAM) implemented with state-of-the-art bulk FinFETs and silicon-on-insulator (SOI) gate-all-around nanosheet transistors (NSFETs) for G40M16/T2 (2 nm) process node. Compared to the FinFET 6T SRAM whose pull-up (PU), pass-gate (PG), and pull-down (PD) transistor footprint (device layout width) ratio can only be either PU:PG:PD = 1:1:2 or 1:2:2, the PU:PG:PD of NSFET SRAM can be 1:α:2, where α can be any number between 1 and 2 owing to the adjustable channel widths of PG transistors . The optimal read and write static noise margin (RSNM and WSNM) design is PU:PG:PD = 1:1.458:2, where the RSNM = WSNM = 171 mV, which is 14% and 51% higher than the minimum RSNM and WSNM values of 1:1:2 and 1:2:2 FinFET SRAMs respectively. Moreover, because the entire device above the SOI substrate of the SOI NSFET can conduct current, its drive current is 109% higher than that of bulk FinFET, in which the part of the device above the silicon substrate forms a punch-through stopper, which does not contribute to the conductive current. In addition, the read/write access time of NSFET SRAM is 49%/7% faster than that of the bulk FinFET SRAM under a 1:2:2 design owing to the higher drive current.

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In/Sb halo doping and replaced anneal sequence for 80 nm CMOS 1

In/Sb halo doping and replaced anneal sequence for 80 nm CMO...

引用

1st International Workshop on Junction technology, IWJT 2000

作者： Toyoshima, Y. Miyashita, K. Morifuji, E. Nakayama, T. Yoshimura, H. System LSI Research and Development Center Toshiba Corporation Semiconductor Company Isogo-ku YokohamaKanagawa235-8522 Japan Advanced Logic Technology Department System LSI Division Toshiba Corporation Semiconductor Company 8 Shinsugita-cho Isogo-ku YokohamaKanagawa235-8522 Japan

ISBN: (纸本)4891140089

Doping techniques for substrate/well, halo structure and shallow extensions were investigated regarding MOSFET miniaturization. Application of heavy ions of antimony and indium for steep retrograde substrate/well and halo structure was examined. For pMOSFET, highly angled antimony ion implantation was found effective to control short channel effect (SCE) with high drive current and low junction leakage current. In contrast, for nMOSFET, indium halo structure was not necessarily effective to control SCE. Detailed understanding of indium diffusion behavior is required. Extension doping sequence was also examined from the process integration point of view. To minimize the thermal budget for extensions, source and drain formation sequence was re-constructed. Highly activated gate electrode and shallow extensions were obtained simultaneously with Co SALICIDE process compatibility. © 2000 Japan Soc. Of Applied Physics.

关键词： Ion implantation

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