检索结果-内蒙古大学图书馆

作者： Hongo, C. Tomita, M. Takenaka, M. Suzuki, M. Murakoshi, A. Corp. Res. and Development Center Toshiba Corporation 1 Komukai Toshiba-cho Saiwai-ku Kawasaki 212-8582 Japan Corp. Res. and Development Center Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan Advanced Logic Technology Department Semiconductor Company Toshiba Corporation 3500 Ooaza-Matsuoka Ooita 870-0197 Japan

The depth profiling for ultrashallow implants using backside secondary ion mass spectrometry (SIMS) was discussed. It was found that the backside SIMS provided sharp B profiles suitable for analyzing ultrashallow implants, even in the case where primary ion energy was used in comparison with implantation energy. The analysis suggested the application of SIMS technique for the development of next-generation devices.

关键词： Ion implantation

来源：评论

学校读者我要写书评

暂无评论

Reliability Characterization for 12 V Application Using the 22FFL FinFET technology

Reliability Characterization for 12 V Application Using the ...

引用

Annual International Symposium on Reliability Physics

作者： C.-Y. Su M. Armstrong S. Chugh M. El-tanani H. Greve H. Li M. Maksud B. Orr C. Perini J. Palmer L. Paulson S. Ramey J. Waldemer Y. Yang D. Young Logic Technology Development Quality and Reliability Intel Corp. Hillsboro Oregon U.S.A. Portland Technology Development Department Intel Corp. Hillsboro Oregon U.S.A. Device Development Group Intel Corp. Hillsboro Oregon U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

引用

IEEE International Test Conference

作者： B.S. Gill C. Papachristou F.G. Wolff N. Seifert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH USA Logic Technology Development Q&R Intel Corporation Hillsboro OR USA

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits

关键词： Sensitivity analysis CMOS logic circuits Timing Libraries Computational modeling Circuit simulation Automatic logic units logic testing Automatic test pattern generation Single event upset

来源：评论

学校读者我要写书评

暂无评论

A robust numerical pole-extraction algorithm for stratified medium

A robust numerical pole-extraction algorithm for stratified ...

引用

IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Y.C. Pan W.C. Chew Logic Technology Development Microprocessor Design Group Intel Corporation Hillsboro OR USA Computational Electromagnetics Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign IL USA

Recent advances in VLSI technology heighten the need to accurately characterize three-dimensional (3D) complex interconnect structures embedded in a layered dielectric medium. Fast evaluation of the multilayer Green's function is often the key in developing an integral equation based algorithm to tackle this problem. Some of the existing pole extraction algorithms are geometry dependent. In This work we present a refined pole extraction algorithms that was conceived for finding poles in a general stratified medium at an arbitrary frequency.

关键词： Robustness Integral equations logic design Microprocessors Computational electromagnetics Very large scale integration Dielectrics Nonhomogeneous media Green function Frequency

来源：评论

学校读者我要写书评

暂无评论

X-ray photoemission investigation of the beryllium oxide band alignment with magnesium oxide and estimates for other insulating and conducting oxides 239

X-ray photoemission investigation of the beryllium oxide ban...

引用

239th ECS Meeting with the 18th International Meeting on Chemical Sensors, IMCS 2021

作者： Koh, D. Hudnall, T.W. Bielawski, C.W. Banerjee, S.K. Brockman, J. Kuhn, M. King, S.W. Microelectronics Research Center Department of Electrical and Computer Engineering University of Texas at Austin 10100 Burnet Road AustinTX78758 United States Department of Chemistry and Biochemistry Texas State University San MarcosTX78666 United States Ulsan44919 Korea Republic of Ulsan44919 Korea Republic of Ulsan44919 Korea Republic of Logic Technology Development Intel Corporation HillsboroOR97124 United States

ISBN: (纸本)9781607689164

Beryllium oxide (BeO) is a wurtzite structured, large bandgap (Eg > 8 eV) material of significant interest as an alloying agent and cladding dielectric in various oxide based optoelectronic devices. The success of such devices is highly reliant on bandgap and band alignment engineering to achieve sufficient charge carrier and optical confinement for device operation. In this regard, we have utilized x-ray photoemission spectroscopy (XPS) to determine the valence band offset (VBO) between atomic layer deposited (ALD) BeO and a (001) oriented magnesium oxide (MgO) substrate. The BeO VBO with MgO (001) was determined to be 0.1 ± 0.15 eV. Applying the rules of commutativity and transitivity for band alignment, we additionally predict the BeO VBO with other conductive oxides such as ZnO, Ga2O3, and InGaZnO4, to be 1.15 ± 0.3 eV, 0.3 ± 0.2 eV, and 0.9 ± 0.2 eV, respectively. © The Electrochemical Society

关键词： II-VI semiconductors

来源：评论

学校读者我要写书评

暂无评论

On-chip optical clock signal distribution

On-chip optical clock signal distribution

引用

Optics in Computing, OC 2003

作者： Zheng, J.-F. Robertson, F.H. Mohammed, E. Young, I. Ahn, D. Wada, K. Michel, J. Kimerling, L.C. Strategic Technology Intel Corporation M/S SC1-03 3065 Bowers Ave Santa ClaraCA95052 United States Strategic Technology Intel Corporation M/S AN 1 AustinTX78746 United States Component Research Intel Corporation HillsboroOR97124 United States Advanced Circuit and Technology Integration Logic Technology Development Intel Corporation HillsboroOR97124 United States Department of Materials Science and Engineering MIT 77 Massachusetts Ave CambridgeMA02139 United States

SiOxNy waveguide-based optical clocking signal distributions with 64-nodes were fabricated in 3mmx5mm Silicon chip area. The network circuitry consists of 3-levels of waveguide H-trees with decreasing bending radii. A... 详细信息

ISBN: (纸本)1557527504

关键词： Optical fiber communication

来源：评论

学校读者我要写书评

暂无评论

Electromigration modeling for design rule development in microelectronic interconnects

引用

AIP Conference Proceedings 1999年第1期491卷 51-61页

作者： Robert J. Gleixner William K. Meyer William D. Nix 1Logic Technology Development Intel Corporation Hillsboro Oregon 97124-5503 2Department of Electrical and Computer Engineering Oregon Graduate Institute Portland Oregon 97291 3Department of Materials Science and Engineering Stanford University Stanford California 94305-2205

The use of a physically-based electromigration model as a means of validating design rules in aluminum-based microelectronic interconnects is presented. This model consider the migration of atoms through the line when driven by an applied current and mechanical stress gradients. The model is then applied to a specific interconnect geometry common to CMOS logic circuits. Here the saturation resistance in the interconnect is shown to agree well with experimental observations. The value of the effective charge (Z*) in this material is found to be −8.8. These results demonstrate the usefulness of electromigration modeling as a means of developing interconnect design rules.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Range based model for technology requirements: Hybrid vehicle technology assessment case study

引用

International Journal of Automotive technology and Management 2007年第4期7卷 314-326页

作者： Jordan, Stephen W. Daim, Tugrul U. Department of Engineering and Technology Management Maseeh College of Engineering and Computer Science Portland State University P.O. Box 751 Portland OR 97207 United States Portland State University ETM Department Intel Corporation Logic Technology Development Group Department of Engineering Technology Management Maseeh College of Engineering and Computer Science Portland State University PSU

This paper presents a performance based technology assessment model. The model was used in a case study aimed at improving the performance (mpg) of a basic hybrid vehicle. The assessment model and case study included a gap analysis, a scouting report for candidate technologies, a technology evaluation and selection model, implementation recommendations, and a diffusion and adoption analysis. Hybrid vehicles are an emerging innovation in vehicle manufacturing that can potentially reduce the amount of carbon emissions associated with 'mainstream' vehicles. Copyright © 2007 Inderscience Enterprises Ltd.

关键词： Mathematical models

来源：评论

学校读者我要写书评

暂无评论

Atomic Layer Deposited Hybrid Organic-Inorganic Aluminates as Potential Low-k Dielectric Materials

引用

MRS Online Proceedings Library (OPL) 2015年第1期1791卷 15-20页

作者： Karina B. Klepper Ville Miikkulainen Ola Nilsen Helmer Fjellvåg Ming Liu Dhanadeep Dutta David Gidley William Lanford Liza Ross Han Li Department of Chemistry Center for Materials Science and Nanotechnology University of Oslo Oslo Norway Department of Physics University of Michigan Ann Arbor MI U.S.A. Department of Physics University of Albany Albany NY U.S.A. Logic Technology Development Intel Corporation Hillsboro OR U.S.A.

The material properties of atomic layer deposited hybrid organic-inorganic aluminate thin films have been evaluated for potential low dielectric constant (i.e. low-k) applications. The hybrid aluminates were deposited using trimethyl aluminum and various linear and aromatic carboxylic acids. The observed electrical and mechanical properties for the hybrid aluminate films varied greatly depending on the selected organic acid with k values ranging from 2.5 to 5.1 and Young’s modulus ranging from 6 to 40 GPa. Leakage currents as low as 4 x 10-10 A/cm2 (at 2 MV/cm) were obtained for films grown using saturated linear carboxylic acids. These results suggest the potential of ALD hybrid aluminate thin films for low-k dielectric applications.

关键词： atomic layer deposition dielectric elastic properties

来源：评论

学校读者我要写书评

暂无评论

A fast multipole method for embedded structure in a stratified medium

引用

Progress in Electromagnetics Research 2004年 44卷 1-38页

作者： Pan, Y.C. Chew, W.C. Logic Technology Development Microprocessor Design Group Intel Corporation Hillsboro OR 97124-6461 United States Center for Computational Electromagnetics and Electromagnetics Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana IL 61801-2991 United States

An efficient, static fast multipole method (FMM) based algorithm is presented in this paper for the evaluation of the parasitic capacitance of 3-D microstrip signal lines embedded in stratified dielectric media. The effect of dielectric interfaces on the capacitance matrix is included in the stage of FMM when outgoing multipole expansions are used to form local multipole expansions. The algorithm retains O(N) computational and memory complexity of the free-space FMM, where N is the number of conductor patches.

关键词： Capacitance

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：