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7th International Conference on Semiconductor technology, ISTC 2008

作者： Ruipeng, Yang Jiaxiang, Nie Yun, Kang Weiye, He Na, Su Bonfanti, Paolo Yuhui, Hu Logic Technology Development Department Semiconductor Manufacturing International Corp. Beijing Economic-Technological Development Area No. 18 Wenchang Road China

ISBN: (纸本)9789881740816

Smaller size copper lines which are widely used in sub-65nm process suffer more serious void defects. Aiming at this problem we did some research about the void defects generated in narrow metal line after chemical mechanical polishing (CMP). SAS DOE(design of experiment) software was applied in this study and the result showed that the ECP current, seed thickness and anneal temperature strongly affected the void existence. We did further research of these key factors, analyzed the mechanism and gave new scheme that can improve the copper void condition at a low risk.

关键词： Copper

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Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments

Multi-cell upset probabilities of 45nm high-k + metal gate S...

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Annual International Symposium on Reliability Physics

作者： N. Seifert B. Gill K. Foley P. Relangi Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Architecture for Quality and Reliability Intel Corporation Hillsboro OR USA Design and Technology Solutions Intel Corporation Hillsboro OR USA Department of Electrical Engineering University of Stanford Stanford CA USA

Multi-cell soft errors are a key reliability concern for advanced memory devices. We have investigated single-bit (SBU) and multi-cell upset (MCU) rates of SRAM devices built in a 45 nm high-k + metal gate (HK+MG) technology under neutron, proton and heavy-ion radiation. Our data highlight the excellent soft error reliability scaling properties of HK+MG. MCU rates were kept at 10% or less of SBU ones and bit-level SBU rates continue to decrease 2times per technology generation for terrestrial applications. SRAM upset rates in orbit are projected to be 2 to 4 orders of magnitude higher than at sea-level. A dramatic increase in MCU rates relative to SBU is projected for geosynchronous orbits, where direct ionization by heavy-ions dominates. No indication of charge amplification by parasitic bipolar devices has been observed for all investigated radiation environments. The observation that SBU error rates and small MCU error rates are elevated at locations in close proximity to well contacts for high LET values is speculated to be the result of the formation of a funnel between well contacts and sensitive drains.

关键词： High K dielectric materials High-K gate dielectrics Random access memory Error analysis Protons Space technology Neutrons Ionization Error correction codes logic devices

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A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs

A Blind Calibration Technique to Correct Memory Errors in Am...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Munkyo Seo Sopan Joshi Ian A. Young Department of Electrical and Computer Engineering University of California Santa Barbara CA USA Logic Technology Development Intel Corporation Hillsboro OR USA

The authors present a statistics-based blind calibration technique for nonlinear memory errors in amplifier-sharing pipelined ADCs. The proposed method is fully digital and simple to implement. It detects memory errors in normal operation without system suspension for calibration. No special calibration signal or analog circuitry is necessary. Algorithm description and simulation results are presented. The proposed technique improves the power efficiency of pipelined ADCs by enabling sharing of low-gain operational amplifiers.

关键词： Calibration Error correction Computer errors Circuits Pipelines Operational amplifiers logic arrays Capacitors CMOS technology Energy consumption

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Range based model for technology requirements: Hybrid vehicle technology assessment case study

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International Journal of Automotive technology and Management 2007年第4期7卷 314-326页

作者： Jordan, Stephen W. Daim, Tugrul U. Department of Engineering and Technology Management Maseeh College of Engineering and Computer Science Portland State University P.O. Box 751 Portland OR 97207 United States Portland State University ETM Department Intel Corporation Logic Technology Development Group Department of Engineering Technology Management Maseeh College of Engineering and Computer Science Portland State University PSU

This paper presents a performance based technology assessment model. The model was used in a case study aimed at improving the performance (mpg) of a basic hybrid vehicle. The assessment model and case study included a gap analysis, a scouting report for candidate technologies, a technology evaluation and selection model, implementation recommendations, and a diffusion and adoption analysis. Hybrid vehicles are an emerging innovation in vehicle manufacturing that can potentially reduce the amount of carbon emissions associated with 'mainstream' vehicles. Copyright © 2007 Inderscience Enterprises Ltd.

关键词： Mathematical models

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The influence of Ar sputter cleaning on NiSi formation and NiSi junction leakage

The influence of Ar sputter cleaning on NiSi formation and N...

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6th International Conference on Semiconductor technology, ISTC2007

作者： Yang, Rui Peng Hu, Yuhui Bonfanti, Paolo Su, Na Nie, Jiaxiang Kang, Yun Logic Technology Development Department Semiconductor Manufacturing International Corp. Economic-Technological Development Area No. 18 Wenchang Road Beijing China

ISBN: (纸本)9889884445

A method to reduce junction leakage for 65 nm products was proposed. The study focused on the impact of Ar sputter cleaning (ASC) on Nickel silicide spiking and junction leakage. It was found by TEM that spiking decrease in PMOS area by eliminating ASC before Ni deposition. As a result, junction leakage was improved. Decreasing Plasma and bias power did not have obvious improvement and spiking still existed. The supposed plasma damage model was not supported by AFM data that Si substrate roughness did not have difference between before and after ASC. Here proposed a new model.

关键词： Silicides

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Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Dev...

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Annual International Symposium on Reliability Physics

作者： N. Seifert P. Slankard M. Kirsch B. Narasimham V. Zia C. Brookreson A. Vo S. Mitra B. Gill J. Maiz Logic Technology Development Q&R Intel Corporation Hillsboro OR USA Department of Electrical Engineering and Computer Science Vanderbilt University Nashville TN USA Enterprise Microprocessor Group Intel Corporation Hillsboro OR USA Digital Enterprise Group Q&R Intel Corporation Hillsboro OR USA Logic Technology Development Q&R Intel Corporation Folsom CA USA Department of Electrical Engineering University of Stanford Stanford CA USA

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs, sequentials and static combinational logic. Our results show that for SRAMs the single-bit soft error rate continues to decrease whereas the multi-bit SER increases dramatically. While the total soft error rate of logic devices (sequentials and static combinational devices) has not changed significantly, a substantial increase in the susceptibility to alpha particles is observed. Finally, a novel methodology to extract one-dimensional cross sections of the collected charge distributions from measured multi-bit statistics is introduced

关键词： Error analysis logic devices Random access memory Neutrons Testing Interleaved codes CMOS logic circuits CMOS technology Microprocessors Alpha particles

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

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IEEE International Test Conference, ITC 2005

作者： Gill, Balkaran S. Papachristou, Chris Wolff, Francis G. Seifert, Norbert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH Logic Technology Development Q and R Intel Corporation Hillsboro OR

ISBN: (纸本)0780390393

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits. © 2005 IEEE.

关键词： CMOS integrated circuits

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Node sensitivity analysis for soft errors in CMOS logic

Node sensitivity analysis for soft errors in CMOS logic

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IEEE International Test Conference

作者： B.S. Gill C. Papachristou F.G. Wolff N. Seifert Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland OH USA Logic Technology Development Q&R Intel Corporation Hillsboro OR USA

In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes using characterization tables and inverse pulse propagation. We generated these tables for every logic cell of the library using Spice simulations for a 100 nm process technology. An additional technique to compute the logic masking of the transistor nodes using an automatic test pattern generation tool is described. Our results show that our approach has Spice like accuracy but it is several orders of magnitude faster than Spice. This approach can be used to analyze the vulnerability of circuits to single event upsets at the chip level. Results are provided for ISCAS85 benchmark circuits

关键词： Sensitivity analysis CMOS logic circuits Timing Libraries Computational modeling Circuit simulation Automatic logic units logic testing Automatic test pattern generation Single event upset

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Radiation-induced clock jitter and race

Radiation-induced clock jitter and race

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Seifert, Norbert Shipley, Paul Pant, Mondira Deb Ambrose, Vinod Gill, Balkaran Logic Technology Development Q and R Intel Corporation 5200 N. E. Elam Young Parkway Hillsboro OR 97124-5503 EPD Design Intel Corporation 1600 Juillete Lane Santa Clara CA 95052 MMDC Design Intel Corporation 77 Reed Road Hudson MA 01749 Department of Computer Engineering Case Western Reserve University Cleveland OH 44106

ISBN: (纸本)0780388038

This study assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20x improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty. © 2005 IEEE.

关键词： Electric clocks

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A novel approach for the patterning and high-volume production of Sub-40-nm gates

A novel approach for the patterning and high-volume producti...

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作者： Romero, Karla Stephan, Rolf Grasshoff, Gunter Mazur, Martin Ruelke, Hartmut Huy, Katja Klais, Jochen McGowan, Sarah Dakshina-Murthy, Srikanteswara Bell, Scott Wright, Marilyn Fab36 01109 Dresden Germany Saxony 01109 Dresden Germany Sunnyvale CA 94088 United States Singapore 469032 Singapore 300 mm Fab36 Dresden Germany Fab36 Dresden Germany Fab36 Dresden Germany FEOL Etch Process Engineering Group FEOL Process Development 300-mm Facility Dresden Germany CVD and PVD Projects AMD's FAB30 Thin Films Group FAB30 Saxony Dresden Germany Defect Yield Enhancement Group in Fab30 Department Sunnyvale CA AMD Singapore Advanced Process Development Group Sunnyvale CA Logic Technology Development AMD's Sunnyvale CA

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility. © 2005 IEEE.

关键词： Gates (transistor)

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