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Density and atomic coordination dictate vibrational characteristics and thermal conductivity of amorphous silicon carbide

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Physical Review Materials 2022年第9期6卷 094601-094601页

作者： Sandip Thakur Connor Jaymes Dionne Pravin Karna Sean W. King William Lanford Han Li Shouvik Banerjee Devin Merrill Patrick E. Hopkins Ashutosh Giri Department of Mechanical Industrial and Systems Engineering University of Rhode Island Kingston Rhode Island 02881 USA Intel Corporation Logic Technology Development Hillsboro Oregon 97124 USA Physics Department University at Albany Albany New York 12206 USA Department of Mechanical and Aerospace Engineering University of Virginia Charlottesville Virginia 22904 USA Department of Materials Science and Engineering University of Virginia Charlottesville Virginia 22904 USA Department of Physics University of Virginia Charlottesville Virginia 22904 USA

Silicon carbide coatings and thin films are used for a wide array of applications ranging from thermal barrier coatings to microelectronics. In this paper, we report on the role of mass density and atomic coordination on the fundamental vibrational characteristics and thermal conductivity of amorphous silicon carbide systems through a combination of experiments and systematic atomistic simulations. We use time domain thermoreflectance to show that the thermal conductivity of hydrogenated amorphous silicon carbide can be increased twofold with ∼40% increase in the mass density. A simple description of thermal transport applicable to a range of amorphous solids where diffusion of thermal energy is predominantly driven by nonpropagating modes cannot fully describe our experimental measurements. Our molecular dynamics simulations in conjunction with our lattice dynamics calculations shed light on the intrinsic role of atomic coordination in dictating the contributions from both propagating and nonpropagating modes in amorphous silicon carbide structures. More specifically, we find that as the concentration of sp3 hybridized carbon atoms is increased by up to 10% with increasing mass densities, the contribution from propagons can be increased from ∼25% to ∼40%, after which further increments in the mass density and the sp3 fraction does not lead to higher contributions from propagons. In contrast, contributions from the nonpropagating modes increases monotonically with increasing mass density and sp3 hybridization. Our results pave a path forward to manipulate the thermal conductivity of amoprhous silicon carbide systems based on varying the atomic coordination.

关键词： Hardness Thermal conductivity Amorphous semiconductors

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Modeling substrate diodes under ultra high ESD injection conditions

Modeling substrate diodes under ultra high ESD injection con...

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Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

作者： Gianluca Boselli Sridhar Ramaswamy Ajith Amerasekera Ton Mouthaan Fred Kuper Logic Technology Development Texas Instruments Inc. Dallas TX USA Department of Electrical Engineering MESA Research Institute University of Twente Netherlands ASIC Circuit Design Texas Instruments Inc. Dallas TX USA Philips Semiconductors GmbH Netherlands

In this paper the behavior of P + -N - -N + substrate diodes under ultra high injection conditions will be analyzed both numerically and experimentally. The J(V) characteristic in this regime will be analytically obtained, modeled and verified both on numerical simulations and on measured devices. For modeling purposes, an analytical fitting law matching the J(V) characteristic over a broad range of injection levels will be proposed. Self-heating effects and process/layout variations will be analyzed too.

关键词： Electrostatic discharge Substrates Semiconductor diodes Protection Instruments Circuits CMOS technology Bipolar transistors Electrons Conductivity

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A novel approach for the patterning and high-volume production of Sub-40-nm gates

A novel approach for the patterning and high-volume producti...

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作者： Romero, Karla Stephan, Rolf Grasshoff, Gunter Mazur, Martin Ruelke, Hartmut Huy, Katja Klais, Jochen McGowan, Sarah Dakshina-Murthy, Srikanteswara Bell, Scott Wright, Marilyn Fab36 01109 Dresden Germany Saxony 01109 Dresden Germany Sunnyvale CA 94088 United States Singapore 469032 Singapore 300 mm Fab36 Dresden Germany Fab36 Dresden Germany Fab36 Dresden Germany FEOL Etch Process Engineering Group FEOL Process Development 300-mm Facility Dresden Germany CVD and PVD Projects AMD's FAB30 Thin Films Group FAB30 Saxony Dresden Germany Defect Yield Enhancement Group in Fab30 Department Sunnyvale CA AMD Singapore Advanced Process Development Group Sunnyvale CA Logic Technology Development AMD's Sunnyvale CA

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility. © 2005 IEEE.

关键词： Gates (transistor)

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Long retention time of embedded DRAM macro with thin gate oxide film transistors

Long retention time of embedded DRAM macro with thin gate ox...

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IEEE Asia-Pacific Conference on ASIC (AP-ASIC)

作者： R. Fukuda S. Miyano T. Namekawa R. Haga O. Wada S. Takeda K. Numata M. Habu H. Koike H. Takato System LSI Research and Development Center Toshiba Corporation Semiconductor Company Kawasaki Japan System LSI Test and Packaging Department Toshiba Corporation Semiconductor Company Kawasaki Japan Advanced Logic Technology Department Toshiba Corporation Semiconductor Company Kawasaki Japan System LSI Design Infrastructure Department Toshiba Corporation Semiconductor Company Kawasaki Japan

This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as well as the macros with the conventional WL architecture. We found the retention time of the negative WL architecture is longer by more than 5 times than that of the conventional WL architecture.

关键词： Random access memory Transistors Large scale integration Impurities logic testing Application specific integrated circuits Variable structure systems Threshold voltage CMOS technology Decoding

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Fundamentals of Cu/Barrier-Layer Adhesion in Microelectronic Processing

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MRS Online Proceedings Library 2005年第1期863卷 B9.2-1-B9.2-6页

作者： Harsono Simka Sadasivan Shankar Carolyn Duran Michael Haverty Technology CAD Department Logic Technology Development USA Storage Technologies Group Technology and Manufacturing Group Intel Corporation Santa Clara USA

Copper is most widely used interconnect material in present silicon microelectronic technologies. As such, multiple interfaces formed by a thin Cu layer and other materials must be engineered to achieve the desired chemical, mechanical, and electrical properties. Adhesion between Cu and the barrier layer, as well as between Cu and the dielectric, is of particular interest, due to its role in controlling interfacial stability and Cu electromigration behavior [1]. This work focuses on understanding how the interface chemistry affects adhesion. Firstprinciples density functional theory (DFT) calculations were used to determine chemical adhesion energies of interfaces formed by Cu and various metals considered as a diffusion barrier, including Ta, TiN, and W. Calculations predicted increasing adhesion strength in the order of TiN < Si-doped TiN < TaN < Ta, consistent with wetting experiments done using 100Å thick Cu layer samples. The effects of doping at the interface using light elements (C, N, O) were also determined. Calculations were also done for interfaces of Cu with two different classes of amorphous dielectric materials, i.e. silicon nitride and silicon carbide, for which detailed material characterizations are often difficult and time consuming. Calculations predicted Cu/Si-nitride and Cu/Si-carbide adhesion strengths consistent with 4-pt-bend experiments, including the improvement in adhesion energies when silicon was used to dope the interface. In addition, weaker interfaces provide low-resistance diffusion paths for Cu atoms during electromigration. The first-principles based modeling, validated by select adhesion measurements, provides a predictive approach to effectively determine adhesion strengths and predict electromigration reliability in interconnects.

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Characterization of Porous BEOL Dielectrics for Resistive Switching

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ECS Meeting Abstracts 2016年第16期MA2016-01卷

作者： Ye Fan Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech

Building nonvolatile memory directly into a CMOS low-k/Cu interconnects would reduce latency in connectivity constrained computational devices and reduce chip's footprint by stacking memory on top of logic. In the relentless drive to lower the interconnect time delay, porous low-k dielectrics are being currently explored. In this paper, porous dielectrics are being electrically characterized and their suitability for resistive switching (RS) assessed. Metal-Insulator-Metal (MIM) structures have been manufactured with bottom Cu electrode and with top island-shaped W or Pt counter-electrode. The porous dielectric was a-SiC:H or a-SiOC:H with level of porosity varying between 8% to 25%. The thickness of the porous dielectric is 20 nm and the dielectric constant k varied between 3.1 (@ 8% porosity) and 2.5 (@25% porosity). Some devices have a 2 nm SiCN diffusion barrier (DB), either at the Cu or W/Pt electrode or at both electrodes. The SiCN layers serve a dual-purpose: i) to prevent Cu diffusion, and ii) to prevent Cu, W, and Pt protrusion into pores and voids of porous dielectrics. A bulk majority of devices has been found conductive from the beginning and less than 10% - only those with at least one DB - displayed RS behavior. The intrinsic conductive state has been found to scale with the area of the top island electrode, and its temperature coefficient of resistance (TCR) has been found to be TCR=0.0028 K-1. Both findings are consistent with high concentration of Cu in the dielectric indicating bulk conduction. This means that porous dielectrics are vulnerable to metal diffusion and even two diffusion barriers of 2 nm are marginal in arresting Cu diffusion. When subjected to resistive switching, the intrinsic resistance Rint was found to be dependent on the applied compliance current Icc. Rint decreases linearly with increasing Icc when Icc is smaller than a critical value Icc(crit), typically 10 mA; for Icc larger than Icc(crit) Rint is constant. This finding is e

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Characterization of Porous BEOL Dielectrics for Resistive Switching

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ECS Transactions 2016年第2期72卷

作者： Ye Fan Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech

Porous back-end dielectric materials with porosity ranging from 8% to 25% have been characterized in terms of their resistive switching behavior. The porous dielectric is sandwiched between Cu and W or Pt electrodes. Some metal-insulator-metal structures have a 2 nm SiCN diffusion barrier at either electrode or at both electrodes. 90% of samples are intrinsically conductive due to strong Cu doping of the dielectric. About 10% of the samples display resistive switching behavior, of which devices with two SiCN barriers can be switched repeatedly, demonstrating that resistive switching in porous dielectrics is feasible. The forming voltage of the filaments increases with increasing porosity of the dielectric. Depending on the voltage polarity, Cu and oxygen vacancy conductive filaments can be formed. The properties of resistive switching established in this work provide a solid basis for further improvement of ReRAM devices based on porous dielectrics compatible with CMOS backend.

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Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics

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ECS Meeting Abstracts 2016年第16期MA2016-01卷

作者： Ye Fan Rizwan Ali Sean W. King Jeff Bielefeld Marius K Orlowski Virginia Tech ECE Department Virginia Tech Intel Corporation Intel Inc Logic Technology Development Lab ECE Department Virginia Tech

In an effort to lower the interconnect time delay and address the latency problem, porous low-k dielectrics are being currently explored as a low-k BEOL dielectric. Because of low density, porous dielectrics suffer from excessive impurity diffusion and from ion electromigration when the interconnect lines are powered. This paper investigates the relation of ion diffusivity and electro-mobility in porous dielectrics. Metal-Insulator-Metal (MIM) structures have been manufactured with bottom Cu electrode and with top island-shaped W or Pt counter-electrode. The porous dielectric was a-SiC:H or a-SiOC:H with level of porosity varying between 8% to 25%. The thickness of the porous dielectric is 20 nm and the dielectric constant k varied between 3.1 (@ 8% porosity) and 2.5 (@25% porosity). Some devices have a 2 nm SiCN diffusion barrier (DB), either at the Cu or W/Pt electrode or at both electrodes. The SiCN layers serve a dual-purpose: i) to prevent Cu diffusion, and ii) to prevent Cu, W, and Pt protrusion into pores and cavities of porous dielectrics. A bulk majority of devices have been found intrinsically conductive, i.e. conductive from the beginning and less than 10% - only those with at least one DB - displayed resistive switching (RS) behavior. Of those devices that showed resistive switching behavior, devices with higher porosity showed consistently higher forming voltage Vform of Cu filaments than dielectrics with lower porosity. This is strange in view of the fact that most of the devices even of high porosity where intrinsically conductive indicating a very high degree of Cu diffusion. For a-SiC:H film with 8% porosity we find Vform ≈ 0V, compared with Vform= 0.4 - 0.5V for 12% porosity and Vform= 1.4 V- 2.3 V for 25% porosity. Why should electromigration require higher electric field when the Cu diffusivity appears to be equally strong? In nonporous materials the diffusivity D and mobility m of charged particles such as an ion is related by the Einstein relat

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Decoupling of Ion Diffusivity and Electromobility in Porous Dielectrics

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ECS Transactions 2016年第2期72卷

Porous back-end dielectric materials with porosity from 8% to 25%, sandwiched between Cu and W/Pt electrodes, have been investigated in terms of Cu diffusivity and mobility. In nonporous materials the diffusivity D and mobility m of charged particles such as an ion is related by the Einstein relation: μ=D q/kT. Here, we present evidence that in porous materials the diffusivity and mobility are decoupled on a global scale, even though the Einstein relation still holds locally. In porous materials, the voids lying in the path of the ion present an impenetrable barrier for ion migration. Voids can be only overcome by a detour around the obstacle by virtue of diffusion. We propose a modified relation between diffusivity and mobility in porous materials by μ=fpD q/kT where a porosity-tortuosity factor fp <1 is introduced. The factor fp depends on porosity and tortuosity of the porous material.

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Radiation-induced clock jitter and race

Radiation-induced clock jitter and race

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Annual International Symposium on Reliability Physics

作者： N. Seifert P. Shipley M.D. Pant V. Ambrose B. Gill Logic Technology Development Q&R Intel Corporation Hillsboro OR USA EPD Design Intel Corporation Santa Clara CA USA MMDC Desien Intel Corporation Hudson MA MMDC Desien Intel Corporation Hudson MA USA Department of Computer Engineering Case Western Reserve University Cleveland OH USA Intel Corporation Hillsboro OR

The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.

关键词： Clocks Jitter Single event upset Error analysis SPICE Microprocessors Pulse generation Radiation hardening Neutrons Modems

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