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East-West Design & Test Symposium (EWDTS)

作者： Vazgen Melikyan Arthur Sahakyan Arsen Hekimyan Davit Trdatyan Aram Shishmanyan Tigran Khazhakyan Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan Armenia National Research University of Electronic Technology Moscow Russia European Regional Academy Yerevan Armenia

A low power method of clock signal duty cycle adjustment is presented in this paper. The proposed architecture produces a synchronous signal in the output of system with 50±1% duty cycle over PVT, which is needed to avoid data error and setup/hold time margins violations during farther operation with data. Method also helps to improve noise immunity, because in case of 50% duty cycle signal in the input of synchronous system makes it more noise protected and helps to avoid phase errors between control signals. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB) and some structures of ADC/DACs.

关键词： Detectors Clocks Distortion Integrated circuit modeling Switches Capacitors Universal Serial Bus

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Self-calibration method for input/output termination resistance variation elimination

Self-calibration method for input/output termination resista...

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2014 IEEE 34th International Scientific Conference on Electronics and Nanotechnology, ELNANO 2014

作者： Vazgen, Sh. Melikyan Ani, L. Aleksanyan Vache, A. Galstyan Ani, S. Harutyunyan Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan Armenia

ISBN: (纸本)9781479945801

A method of on-die resistance self-calibration for receiver and transmitter Input/Output devices, without external reference resistor is presented. Resistance mismatch elimination method, using reference clock and dc current is provided. The proposed method provides opportunity to measure the difference of the termination resistor and the transmission line impedance which is assumed 50-Ohm, detect the variation and minimizing it. A self-calibration technique for termination resistors mismatch elimination is implemented. © 2014 IEEE.

关键词： Resistors

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High PSRR and accuracy receiver active equalizer

High PSRR and accuracy receiver active equalizer

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2014 IEEE 34th International Scientific Conference on Electronics and Nanotechnology, ELNANO 2014

作者： Vazgen, Sh. Melikyan Arthur, S. Sahakyan Dingchyan Hayk, H. Nazeli, V. Melikyan Ani, L. Aleksanyan Armen, S. Sahakyan Vahe, S. Babayan Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan Armenia Department of Control and Informatics in Technical Systems State Engineering University of Armenia Yerevan Armenia

ISBN: (纸本)9781479945801

High accuracy equalization and high power supply rejection ratio equalizer in the receiver of a high-speed serial link presented. To validate the proposed architecture, conducted experiments, for examples, with various injected faults, for which the conventional approach of examining the eye opening at the output of the equalizer results. Proposed equalizer have supply noise with 35% higher rejection ratio than USB specification required and hence this equalization mechanism can be used in the special input/output circuits of Universal Serial Bus (USB) and some other protocols as well. © 2014 IEEE.

关键词： Equalizers

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Resistance calibration method without external precision elements

Resistance calibration method without external precision ele...

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East-West Design & Test Symposium (EWDTS)

作者： Vazgen Melikyan Arthur Sahakyan Mikayel Piloyan Gagik Hovhannisyan Aram Shishmanyan Taron Hovhannisyan Davit Trdatyan Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan Armenia

A method of resistance calibration without external precision elements usage presented in paper. In the proposed method, used structures which operation based on technologically accurate elements and signals to have high accuracy resistance after calibration. Architecture produces a calibration code corresponding to 50Ohms PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. Standard calibration methods using external ~1% accuracy precision discreet resistance (50 or 200Ohms). The presented calibration mechanism using internal elements and can provide ~ 4-7% accuracy of calibration. Method can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

关键词： Calibration Resistance Accuracy Capacitors Resistors Receivers Reflection

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Self-calibration method for input/output termination resistance variation elimination

Self-calibration method for input/output termination resista...

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IEEE International Conference on Electronics and Nanotechnology (ELNANO)

作者： Sh. Melikyan Vazgen L. Aleksanyan Ani A. Galstyan Vache S. Harutyunyan Ani Department of Microelectronics Circuits and Systems State Engineering University of Armenia Yerevan Armenia Synopsys Armenia CJSC

关键词： Resistance Resistors Binary codes Operational amplifiers Integrated circuits Reflection Switches

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25th Annual Computational Neuroscience Meeting CNS-2016, Seogwipo City, South Korea, July 2-7, 2016 Abstracts

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BMC NEUROSCIENCE 2016年第1期17卷 1-112页

作者： [Anonymous] Computational Neurobiology Laboratory The Salk Institute for Biological Studies San Diego USA UNIC CNRS Gif sur Yvette France The European Institute for Theoretical Neuroscience (EITN) Paris France ATR Computational Neuroscience Laboratories Kyoto Japan Krembil Research Institute University Health Network Toronto Canada Department of Physiology University of Toronto Toronto Canada Department of Medicine (Neurology) University of Toronto Toronto Canada Department of Physics University of New Hampshire Durham USA Department of Neurophysiology Nencki Institute of Experimental Biology Warsaw Poland Department of Theory Wigner Research Centre for Physics of the Hungarian Academy of Sciences Budapest Hungary Department of Mathematical Sciences KAIST Daejoen Republic of Korea Department of Mathematics University of Houston Houston USA Department of Biochemistry & Cell Biology and Institute of Biosciences and Bioengineering Rice University Houston USA Department of Biology and Biochemistry University of Houston Houston USA Grupo de Neurocomputación Biológica Dpto. de Ingeniería Informática Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Department of Biological Sciences University of Southern California Los Angeles USA Center for Neuroscience Korea Institute of Science and Technology Seoul South Korea Department of Neurology Albert Einstein College of Medicine Bronx USA Center for Neuroscience KIST Seoul South Korea Department of Neuroscience University of Science and Technology Daejon South Korea Systems Neuroscience Group QIMR Berghofer Medical Research Institute Herston Australia Department of Psychology Yonsei University Seoul South Korea Department of Psychiatry Kyung Hee University Hospital at Gangdong Seoul South Korea Department of Psychiatry Veterans Administration Boston Healthcare System and Harvard Medical School Brockton USA Department of Electrical and Electronic Engineering The University of Melbourne Parkvil

A1 Functional advantages of cell-type heterogeneity in neural circuits Tatyana O. Sharpee A2 Mesoscopic modeling of propagating waves in visual cortex Alain Destexhe A3 Dynamics and biomarkers of mental disorders Mitsuo Kawato F1 Precise recruitment of spiking output at theta frequencies requires dendritic h-channels in multi-compartment models of oriens-lacunosum/moleculare hippocampal interneurons Vladislav Sekulić, Frances K. Skinner F2 Kernel methods in reconstruction of current sources from extracellular potentials for single cells and the whole brains Daniel K. Wójcik, Chaitanya Chintaluri, Dorottya Cserpán, Zoltán Somogyvári F3 The synchronized periods depend on intracellular transcriptional repression mechanisms in circadian clocks. Jae Kyoung Kim, Zachary P. Kilpatrick, Matthew R. Bennett, Kresimir Josić O1 Assessing irregularity and coordination of spiking-bursting rhythms in central pattern generators Irene Elices, David Arroyo, Rafael Levi, Francisco B. Rodriguez, Pablo Varona O2 Regulation of top-down processing by cortically-projecting parvalbumin positive neurons in basal forebrain Eunjin Hwang, Bowon Kim, Hio-Been Han, Tae Kim, James T. McKenna, Ritchie E. Brown, Robert W. McCarley, Jee Hyun Choi O3 Modeling auditory stream segregation, build-up and bistability James Rankin, Pamela Osborn Popp, John Rinzel O4 Strong competition between tonotopic neural ensembles explains pitch-related dynamics of auditory cortex evoked fields Alejandro Tabas, André Rupp, Emili Balaguer-Ballester O5 A simple model of retinal response to multi-electrode stimulation Matias I. Maturana, David B. Grayden, Shaun L. Cloherty, Tatiana Kameneva, Michael R. Ibbotson, Hamish Meffin O6 Noise correlations in V4 area correlate with behavioral performance in visual discrimination task Veronika Koren, Timm Lochmann, Valentin Dragoi, Klaus Obermayer O7 Input-location dependent gain modulation in cerebellar nucleus neurons Maria Psarrou, Maria Schilstra, Neil Davey, Benjamin Torben-Ni

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High accuracy equalization method for receiver active equalizer

High accuracy equalization method for receiver active equali...

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2013 11th IEEE East-West Design and Test Symposium, EWDTS 2013

作者： Melikyan, Vazgen Sh. Sahakyan, Arthur S. Safaryan, Karo H. Dingchyan, Hayk H. Synopsys Armenia CJSC Armenia Department of Microelectronics Circuits and Systems State Engineering University of Armenia VLSI Design Specialization Synopsys Armenia Educational Department Armenia

ISBN: (纸本)9781479920969

A method of high accuracy equalization for linear equalizer in the receiver of a high-speed serial link presented in this paper. To validate the proposed method, we conducted experiments, for examples, with various injected faults, for which the conventional approach of examining the eye opening at the output of the equalizer results. The presented equalization mechanism can be used in the special input/output circuits of Universal Serial Bus (USB). © 2013 IEEE.

关键词： Equalizers

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Data - Clock Setup and Hold Times Margins Correction Method in High Speed Serial Links

Data - Clock Setup and Hold Times Margins Correction Method ...

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International Conference on Computer Science and Information Technologies

作者： Vazgen Sh. Melikyan Arthur S. Sahakyan Aram H. Shishmanyan Nazeli V. Melikyan Grigor Y. Zargaryan Department of Microelectronics Circuits and Systems State Engineering University of Armenia VLSI Design Specialization Synopsys Armenia Educational Department

ISBN: (纸本)9781479924622

A method of serial links output data and clock signals setup and hold times correction presented in this paper. The proposed architecture produces corrected clock which have enough setup/hold time margins respect data signal over PVT, which is needed to avoid data errors and setup/hold violations during further operation with data. The presented correction mechanism can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.

关键词： Serializer Voltage Controlled Delay Line (VCDL) PVT Clock Corrector (CC)

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IPF: In-place X-filling to mitigate soft errors in SRAM-based FPGAs

IPF: In-place X-filling to mitigate soft errors in SRAM-base...

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21st International Conference on Field Programmable Logic and Applications, FPL 2011

作者： Feng, Zhe Jing, Naifeng Chen, Gengsheng Hu, Yu He, Lei Electrical Engineering Department University of California Los Angeles United States School of Microelectronics Shanghai Jiao Tong University China State Key Lab. of Application Specific Circuits and Systems Fudan University Shanghai China Electrical and Computer Engineering Department University of Alberta Canada

ISBN: (纸本)9780769545295

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chiplevel MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm. © 2011 IEEE.

关键词： Radiation hardening

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IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Base...

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International Conference on Field Programmable Logic and Applications

作者： Zhe Feng Naifeng Jing GengSheng Chen Yu Hu Lei He Electrical Engineering Department University of California Los Angeles USA School of Microelectronics Shanghai Jiao Tong University China State Key Laboratory of Application Specific Circuits and Systems Fudan University Shanghai China Electrical and Computer Engineering Department University of Alberta Canada

SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to Single Event Upsets (SEUs). We show that a large portion (40%-60% for the circuits in our experiments) of the total used LUT configuration bits are don't care bits, and propose to decide the logic values of don't care bits such that soft errors are reduced. Our approaches are efficient and do not change LUT level placement and routing. Therefore, they are suitable for design closure. For the ten largest combinational MCNC benchmark circuits mapped for 6-LUTs, our approaches obtain 20% chip level Mean Time To Failure (MTTF) improvements, compared to the baseline mapped by Berkeley ABC mapper. They obtain 3× more chip level MTTF improvements and are 128× faster when compared to the existing best in-place IPD algorithm.

关键词： Table lookup Field programmable gate arrays Integrated circuit interconnections Integrated circuit reliability Observability Helium

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