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Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning

IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers

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IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年第3期44卷 1193-1198页

作者： Shen, Jinyi Yang, Fan Shang, Li Yan, Changhao Bi, Zhaori Zhou, Dian Zeng, Xuan Fudan University State Key Laboratory of Integrated Chips and Systems School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems The School of Computer Science Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems Microelectronics Department Shanghai200433 China University of Texas at Dallas Department of Electrical Engineering DallasTX75080 United States

Bayesian optimization (BO) is more efficient in automatically synthesizing operational amplifier (opamp) topologies compared to conventional methods. However, the design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. To tackle these challenges, this brief introduces ATOM, an automatic opamp topology synthesis framework. We construct a concise design space for behavior-level opamp topologies, consisting of topologies that designers can easily understand. We propose an opamp topology optimization method that incorporates freeze-thaw BO. This method efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times. The source code for ATOM is available at https://***/Jinyi-Shen/ATOM. © 2024 IEEE.

关键词： Thawing

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis 24

Revisiting sensitivity-based analog sizing with derivative-a...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Lyu, Ruiyu Zhao, Aidong Meng, Yuan Zhu, Keren Bi, Zhaori Yan, Changhao Yang, Fan Zhou, Dian Zeng, Xuan State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China Department of Electrical Engineering University of Texas at Dallas RichardsonTX United States

ISBN: (纸本)9798400710773

Current state-of-the-art (SOTA) analog circuit sizing methods predominantly rely on derivative-free algorithms. However, these methods struggle with sample efficiency due to the lack of derivative information, acting as a bottleneck for further advancements. In contrast, classic sensitivity analysis computes partial derivatives of circuit performance with respect to design parameters, enabling efficient first-order optimization. Yet, sensitivity-driven analog sizing has seen limited use due to: 1) accumulated numerical errors from nonlinear devices, and 2) the complex, non-convex nature of circuit optimization problems, which makes local search methods like gradient descent ineffective for global optimization. To address these challenges, this paper equips SOTA analog sizing algorithms with derivative awareness and proposes DarBO, a Derivative-aware Bayesian Optimization method. DarBO uses derivatives from error-suppressed adjoint sensitivity analysis to improve Gaussian process posteriors in local optimization, enhancing convergence with fewer circuit simulations. For global exploration, DarBO adapts a derivative-aware Gaussian mixture model (d-GMM) for region partitioning and a gradient-driven Monte Carlo tree search (d-MCTS) for subregion selection. By bridging classic sensitivity-driven analog sizing with SOTA Bayesian optimization algorithms, DarBO offers an efficient and robust solution for analog circuit sizing. Experimental results show that DarBO achieves up to 5.0 × acceleration in terms of the number of circuit simulations compared to existing first-order and derivative-free optimization methods. © 2024 Copyright is held by the owner/author(s).

关键词： Convex optimization

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Arbitrary hue-brightness structural colors with high saturation generated by anisotropic metasurfaces

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Photonics Research 2025年第3期13卷 772-780页

作者： CHONG WANG HE LI LONGJIE LI XIAO SHANG SHENGQIONG CHEN HUIWEN XUE PEIWEN ZHANG JIEBIN NIU YONGLIANG ZHANG LINA SHI State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences Department of Electronic and Optical Engineering Space Engineering University State Key Laboratory of Semiconductor Physics and Chip Technologies Institute of SemiconductorsChinese Academy of Sciences

Structural colors have always attracted much attention due to important applications in display devices, imaging security certification, optical data storage, and so on. The brightness of structure colors, as the carrier of chiaroscuro information, is the key to making images appear stronger in the spatial and three-dimensional ***, relatively little work has been done on the control of the color brightness, and the reported structures are complex and difficult to fabricate. Here, we demonstrate a low-aspect-ratio anisotropic metasurface consisting of a PMMA film patterned by arrays of elliptical-shaped holes clamped by two thin aluminum films. By utilizing localized surface plasmon resonances, we realize a three-dimensional (3D) HSB (hue, saturation, and brightness)structure color with independent brightness control and enhance the cross-polarization reflection, covering approximately 120%of the s RGB color gamut. It is shown that the ratio of the major and minor axes leads to the independent control of brightness of the structural colors. The nanoprinting of HSB images with smooth brightness transitions is demonstrated through elaborate design of the metasurface geometry parameters and CMOScompatible micro–nano fabrication process. Our findings will facilitate the broad range of 3D nanoprinting and modern advanced display applications.

关键词： Electron beam lithography Localized surface plasmon resonance Optical data storage Scanning electron microscopy Structural color Thin films

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ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Sy...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Hongyang Pan Keren Zhu Fan Yang Zhufei Chu Xuan Zeng State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University Shanghai China Faculty of Electrical Engineering and Computer Science Ningbo University Ningbo China

ISBN: (数字)9783982674100

ISBN: (纸本)9798331534646

Mapping to $k$ -input lookup tables ( $k$ -LUTs) is a critical process in field-programmable gate array (FPGA) synthesis. However, the structure of the subject graph can introduce structural bias, which refers to the dependency of mapping results on the inherent graph structure, often leading to suboptimal results. To address this, we present ELMap, an area-driven LUT mapping framework. It incorporates structural choice during the collapsing phase. This enables dynamic decomposition, maximizing local-to-global optimization transfer. To ensure seamless integration between the optimization and mapping processes, ELMap leverages exact $k$ -LUT synthesis to generate area-optimal sub-LUT networks. Experiments on the EPFL benchmark suite demonstrate that ELMap significantly outperforms state-of-the-art methods. Specifically, in 6-LUT mapping, ELMap reduces the average LUT area by 8.5% and improves the area-depth-product (ADP) by 5.8%. In 4-LUT remapping, it reduces the average LUT area by 17.6% and improves the ADP by 2.4%.

关键词： Europe Benchmark testing Table lookup Logic Optimization Field programmable gate arrays

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Adaptive ILT via Multi-Level Lithography Simulation

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IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年

作者： Sun, Shuyuan Yang, Fan Yu, Bei Shang, Li Zeng, Xuan Fudan University State Key Lab of Integrated Circuits and Systems China Fudan University School of Microelectronics China The Chinese University of Hong Kong Department of Computer Science and Engineering Hong Kong Fudan University School of Computer Science China

Inverse lithography technology (ILT) is an advanced resolution enhancement technology (RET) approach that pushes the limits of current process conditions to achieve smaller feature sizes. This paper presents an efficient ILT framework centered on the concept of solving mask optimization problem from approximation to precision. Firstly, low-resolution lithography simulation is employed to guide ILT, generating a preliminary solution at a low cost. Subsequently, high-resolution lithography simulation is utilized for fine-tuning, and output the final correction results. Additionally, we introduce a continuous correction scheme and a hyperparameter selection strategy to enhance the adaptability and robustness of the ILT solver for full-chip scale layouts. For via layer patterns, we significantly improve the solvers performance by adopting a new high-resolution ILT approach combined with a restricted optimization region. Experimental results show that our method effectively reduces edge placement error (EPE) violations and improves efficiency for ILT on full-chip scale layouts. In the ICCAD 2013 benchmark, our method outperforms state-ofthe-art approaches, reducing L2 loss by at least 1.3%. For via layer patterns, our method achieves a 98% reduction in L2 loss and nearly triples the runtime efficiency compared to its earlier version. Furthermore, it delivers an 8% reduction in L2 loss and a 45% reduction in PVBand compared to other existing methods. © 1982-2012 IEEE.

关键词： Inverse problems

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A Novel Multiple Modes Resonant Sensor Featuring Blue Sideband Excitation 38

A Novel Multiple Modes Resonant Sensor Featuring Blue Sideba...

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38th IEEE International Conference on Micro Electro Mechanical systems, MEMS 2025

作者： Xu, Jiao Zheng, Zhuoyue Xi, Jingqian Zhang, Ziqian Liu, Huafeng Zhang, Pan Chen, Jianlin Wang, Chen Kraft, Michael Wang, Yuan Martins, R.P. Mak, Pui-In Huazhong University of Science and Technology Moe Key Laboratory of Fundamental Physical Quantities Measurement Pgmf School of Physics Wuhan430074 China University of Macau Institute of Microelectronics State Key Laboratory of Analog and Mixed-Signal Vlsi 999078 China Peking University National Key Laboratory of Advanced Micro and Nano Manufacture Technology School of Integrated Circuits 100871 China Shanghai University School of Microelectronics 200444 China Ku Leuven Department of Electrical Engineering-MNS Leuven3000 Belgium

ISBN: (纸本)9798331508890

This paper reports a novel MEMS resonant structure functioning as a baseline resonant electrostatic force/temperature sensor, highlighting its substantial potential in sensing applications. The resonator, characterized by a dual-cosine structure, is capable of simultaneous multiple resonant modes actuation within the 300 kHz range, through a sole-source drive approach using the recent emerging Blue Sideband Excitation (BSE) technique. This method enables a distinctive multi-modal response, essential for multi-parameter measurements. The research focuses on the sensor's temperature characteristics, electrostatic perturbation sensitivity, and noise floor. Notably, the study reveals intriguing temperature responses across different modes, where certain modes exhibit a significant frequency rise with increasing temperature, this is counter-intuitive with common MEMS resonator devices, prompting further investigation into the underlying mechanisms. The analysis of electrostatic perturbation sensitivity and noise background further unfolds the resonator's performance under various excitation conditions, laying a foundation for advancing sensor functionality, and providing solid evidence on the viability of the subject. To sum up, this study highlights the resonator's potential as a high-precision sensor, opening new opportunities for MEMS sensor design and multi-parameter measurement applications. © 2025 IEEE.

关键词： Microchannels

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A Rapid Adaptation Approach for Dynamic Air‑Writing Recognition Using Wearable Wristbands with Self‑Supervised Contrastive Learning

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Nano-Micro Letters 2025年第2期17卷 417-431页

作者： Yunjian Guo Kunpeng Li Wei Yue Nam‑Young Kim Yang Li Guozhen Shen Jong‑Chul Lee Department of Electronic Convergence Engineering Kwangwoon UniversitySeoul 01897South Korea Radio Frequency Integrated Circuit(RFIC)Bio Centre Kwangwoon UniversitySeoul 01897South Korea Department of Electronic Engineering Kwangwoon UniversitySeoul 01897South Korea School of Microelectronics Shandong UniversityJinan 250101People’s Republic of China State Key Laboratory of Integrated Chips and Systems Fudan UniversityShanghai 200433People’s Republic of China School of Integrated Circuits and Electronics Beijing Institute of TechnologyBeijing 100081People’s Republic of China

Wearable wristband systems leverage deep learning to revolutionize hand gesture recognition in daily *** existing approaches that often focus on static gestures and require extensive labeled data,the proposed wearable wristband with selfsupervised contrastive learning excels at dynamic motion tracking and adapts rapidly across multiple *** features a four-channel sensing array composed of an ionic hydrogel with hierarchical microcone structures and ultrathin flexible electrodes,resulting in high-sensitivity capacitance *** wireless transmission from a Wi-Fi module,the proposed algorithm learns latent features from the unlabeled signals of random wrist ***,only few-shot labeled data are sufficient for fine-tuning the model,enabling rapid adaptation to various *** system achieves a high accuracy of 94.9%in different scenarios,including the prediction of eight-direction commands,and air-writing of all numbers and *** proposed method facilitates smooth transitions between multiple tasks without the need for modifying the structure or undergoing extensive task-specific *** utility has been further extended to enhance human–machine interaction over digital platforms,such as game controls,calculators,and three-language login systems,offering users a natural and intuitive way of communication.

关键词： Wearable wristband Self-supervised contrastive learning Dynamic gesture Air-writing Human-machine interaction

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Streamlining Computational Lithography With Efficient Pattern Database

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IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年

作者： Zheng, Su Zhao, Wenqian Sun, Shuyuan Yang, Fan Yu, Bei Wong, Martin D.F. The Chinese University of Hong Kong Department of Computer Science and Engineering Hong Kong Fudan University State Key Lab of Integrated Circuits and Systems China Hong Kong Baptist University Department of Computer Science Hong Kong

In the pursuit of advancing computational lithography, this paper introduces a novel pattern database framework designed to support related tasks. The proposed framework is built upon three core components: an unsupervised metric learning method for robust pattern embedding, a vector database for swift pattern retrieval, and an efficient algorithm dedicated to pattern clustering. These elements synergize to significantly enhance the efficiency and effectiveness of various computational lithography methods. In downstream tasks, our framework provides accurate lithography hotspot detection through pattern retrieval, streamlines inverse lithography technique (ILT) by leveraging solution reusing, and facilitates the exploration of ILT & source parameters based on the pattern clustering results. Collectively, these advancements culminate in a comprehensive improvement in computational lithography, offering a scalable solution for the ever-evolving demands of this field. © 2025 IEEE.

关键词： Inverse problems

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