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Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning

IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年第3期44卷 1141-1154页

作者： Wu, Zheng Shen, Jinyi Yi, Xiaoling Shang, Li Yang, Fan Zeng, Xuan Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Circuits and Systems Shanghai200433 China KU Leuven Department of Electrical Engineering Microelectronics Circuits and Systems Leuven3000 Belgium Fudan University State Key Laboratory of Integrated Circuits and Systems The School of Computer Science Shanghai200433 China

The design space exploration (DSE) of contemporary microprocessors faces a significant challenge of high-computational cost. In this context, we introduce Prior-boosted graph representation learning (GRL), a novel framework for the DSE of the microarchitectures the microprocessors underpinned by graph embeddings. Using GRL, Prior-boosted GRL constructs a compact and continuous vector space for design representation. This framework is further boosted by an efficient sampling algorithm informed by prior knowledge, which is instrumental in generating a superior set of initial designs to accelerate the exploration process. A well-designed ensemble surrogate model is combined with the multiobjective Bayesian optimization to explore the design space holistically within this graph-embedding domain. Rigorous experimental evaluations conducted on the RISC-V Berkeley-Out-of-Order Machine (BOOM) platform demonstrate that Prior-boosted GRL substantially surpasses preceding methods, achieving a 107.79% enhancement in Pareto front quality compared to the state-of-the-art DSE algorithm. It also outstrips manual designs on performance, power, and area metrics. As of this writing, Prior-boosted GRL holds the first place in the ICCAD 2022 CAD Contest evaluation platform. © 2024 IEEE.

关键词： Graph embeddings

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Low Stress TSV Arrays for High-Density Interconnection

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engineering 2024年第7期38卷 201-208页

作者： Binbin Jiao Jingping Qiao Shiqi Jia Ruiwen Liu Xueyong Wei Shichang Yun Yanmei Kong Yuxin Ye Xiangbin Du Lihang Yu Bo Cong Institute of Microelectronics Chinese Academy of SciencesBeijing 100000China School of Integrated Circuits University of Chinese Academy of SciencesBeijing 100000China State Key Laboratory for Manufacturing Systems Engineering Xi’an Jiaotong UniversityXi’an 710049China

In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV *** this study,a novel hollow tungsten TSV(W-TSV)is presented and *** hollow structure provides space for the release of thermal *** results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 *** ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability *** average resistance of the TSV was 1.21 *** leakage current was 643 pA and the breakdown voltage was greater than 100 *** resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV *** results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

关键词： Thermal stress Through-silicon via(TSV)High-density integration

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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

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Science China(Information Sciences) 2024年第10期67卷 100-114页

作者： Shihao HAN Sishuo LIU Shucheng DU Mingzi LI Zijian YE Xiaoxin XU Yi LI Zhongrui WANG Dashan SHANG Department of Electrical and Electronic Engineering The University of Hong Kong ACCESS-AI Chip Center for Emerging Smart Systems InnoHK Centers Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences School of Microelectronics Southern University of Science and Technology

Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

关键词： mixture-of-experts computing-in-memory neural architecture search resistive random-access memory static random-access memory

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Modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

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Chinese Journal of Electronics 2023年第2期32卷 365-374页

作者： YIN Xiangkun WANG Fengjuan ZHU Zhangming Vasilis F.Pavlidis LIU Xiaoxian LU Qijun LIU Yang YANG Yintang Shaanxi Key Lab.of Integrated Circuits and Systems School of Microelectronics Xidian University School of Automation and Information Engineering Xi'an University of Technique Department of Computer Science University of Manchester

Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.

关键词： Semiconductor device modeling Inductance Analytical models Solid modeling Three-dimensional displays Integrated circuit modeling Inductors

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ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers

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IEEE Transactions on Computer-Aided Design of Integrated circuits and systems 2025年第3期44卷 1193-1198页

作者： Shen, Jinyi Yang, Fan Shang, Li Yan, Changhao Bi, Zhaori Zhou, Dian Zeng, Xuan Fudan University State Key Laboratory of Integrated Chips and Systems School of Microelectronics Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems The School of Computer Science Shanghai200433 China Fudan University State Key Laboratory of Integrated Chips and Systems Microelectronics Department Shanghai200433 China University of Texas at Dallas Department of Electrical Engineering DallasTX75080 United States

Bayesian optimization (BO) is more efficient in automatically synthesizing operational amplifier (opamp) topologies compared to conventional methods. However, the design space for behavior-level opamp topologies involves numerous connections that are difficult to comprehend, and evaluating each topology incurs substantial computational costs. To tackle these challenges, this brief introduces ATOM, an automatic opamp topology synthesis framework. We construct a concise design space for behavior-level opamp topologies, consisting of topologies that designers can easily understand. We propose an opamp topology optimization method that incorporates freeze-thaw BO. This method efficiently explores the design space and expedites the evaluation process. Experimental studies demonstrate that ATOM outperforms state-of-the-art topology synthesis methods in terms of success rate and optimization results while reducing the number of required simulations by up to 8.15 times. The source code for ATOM is available at https://***/Jinyi-Shen/ATOM. © 2024 IEEE.

关键词： Thawing

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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Empirical Model and Experimental Validation of Meshed Ground Impact on RF Performance of Flexible Microstrip Lines for Bending Applications

IEEE Journal on Flexible Electronics

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IEEE Journal on Flexible Electronics 2024年第8期3卷 374-382页

作者： Abdelatty, Mohamed Y. Alhendi, Mohammed Obeidat, Abdullah S. Umar, Ashraf Enakerakpo, Emuobosan Al-Haidari, Riadh Poliks, Mark D. State University of New York at Binghamton Department of Systems Science and Industrial Engineering The Center for Advanced Microelectronics Manufacturing BinghamtonNY13902 United States State University of New York at Binghamton The Center for Advanced Microelectronics Manufacturing BinghamtonNY13902 United States

Meshing of conventional printed circuit board (PCB) grounds refers to a process in which certain ground planes appear as copper lattices;regular openings are placed at regular intervals. The need for ground meshing for rigid PCBs has become minor with the development of micro-etching approaches. However, for flexible hybrid electronics (FHEs), meshed grounds could offer some benefits, such as being unsusceptible to bending and conserving material and time. In this article, we study how meshed ground planes affect the radio frequency (RF) performance of straight microstrip lines. Simulations show meshed grounds with more than 50% filling produce good RF performance. When the filling percentage of the meshed grounds is less than 50%, ripples in the insertion loss start to appear. To confirm the simulation results, dispensing and aerosol jet printing (AJP) systems were used to fabricate silver ink microstrip lines on PET substrates with different meshed ground patterns. The experimental measurement confirmed the simulation results. Bend testing was carried out to investigate the impact of mesh grounds on the RF performance of the microstrip lines after bending. The results demonstrate that the less-filled meshed ground samples are less susceptible to bending. As an extension of the work, we developed an empirical model to modify the microstrip line's width to smoothen the insertion loss ripples while maintaining the bending superiority. To experimentally validate the model, predictions from this empirical model were used to fabricate and measure some samples. © 2024 IEEE.

关键词： Substrates

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Large circuit models: opportunities and challenges

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Science China(Information Sciences) 2024年第10期67卷 25-66页

作者： Lei CHEN Yiqi CHEN Zhufei CHU Wenji FANG Tsung-Yi HO Ru HUANG Yu HUANG Sadaf KHAN Min LI Xingquan LI Yu LI Yun LIANG Jinwei LIU Yi LIU Yibo LIN Guojie LUO Hongyang PAN Zhengyuan SHI Guangyu SUN Dimitrios TSARAS Runsheng WANG Ziyi WANG Xinming WEI Zhiyao XIE Qiang XU Chenhao XUE Junchi YAN Jun YANG Bei YU Mingxuan YUAN Evangeline F.Y.YOUNG Xuan ZENG Haoyi ZHANG Zuodong ZHANG Yuxiang ZHAO Hui-Ling ZHEN Ziyang ZHENG Binwu ZHU Keren ZHU Sunan ZOU Huawei Noah’s Ark Lab School of Integrated Circuits Peking University Faculty of Electrical Engineering and Computer Science Ningbo University Department of Electronic and Computer Engineering Hong Kong University of Science and Technology Department of Computer Science and Engineering The Chinese University of Hong Kong School of Integrated Circuits Southeast University Huawei HiSilicon Peng Cheng Laboratory School of Computer Science Peking University School of Microelectronics State Key Laboratory of Integrated Chips and System Fudan University School of Artificial Intelligence Shanghai Jiao Tong University

Within the electronic design automation(EDA) domain, artificial intelligence(AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding,overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level(RTL) designs, circuit netlists,and physical layouts. We champion the creation of large circuit models(LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area(PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.

关键词： AI-rooted EDA large circuit models (LCMs) multimodal circuit representation learning circuit optimization

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Simulating the obstacle avoidance behavior day and night based on the visible-infrared MoS_(2)/Ge heterojunction field-effect phototransistor

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Nano Research 2023年第8期16卷 11296-11302页

作者： Zhao Han Bo Wang Jie You Qiancui Zhang Yichi Zhang Tian Miao Ningning Zhang Dongdong Lin Zuimin Jiang Renxu Jia Jincheng Zhang Hui Guo Huiyong Hu Liming Wang Key Laboratory of Analog Integrated Circuits and Systems Ministry of EducationSchool of MicroelectronicsXidian UniversityXi’an 710071China Qian Xuesen Collaborative Research Center of Astrochemistry and Space Life Sciences Department of Microelectronic Science and EngineeringNingbo UniversityNingbo 315211China Department of Physics Fudan UniversityShanghai 200433China

The contradiction between the high number of visually handicapped people and the scarcity of guide dogs has stimulated the demand for electronic guide dogs(EGDs).Here,we demonstrate an EGD by leveraging piezoresistors on a MoS_(2)/Ge heterostructure for simultaneous pressure-sensing and optical-sensing *** device has excellent gating capability and exhibits large positive and negative photoresponses under visible(532 nm,182 A/W)and infrared(1550 nm,37 A/W)*** characteristics allow the device to efficiently classify different obstacles at all times of day using pressure and light *** device reaches nearly 100%accuracy after 48 training sessions when used to classify frequent *** device adopts passive and active detection modes during the day and night,respectively,which improves the battery life of the *** work provides a significant reference for the future design of EGDs,which may help a greater number of visually impaired people by reducing the cost of such devices.

关键词： electronic guide dogs dual-band photodetection pressure and light synergy work round the clock

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InGaZnO-based photoelectric synaptic devices for neuromorphic computing

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Journal of Semiconductors 2024年第9期45卷 42-47页

作者： Jieru Song Jialin Meng Tianyu Wang Changjin Wan Hao Zhu Qingqing Sun David Wei Zhang Lin Chen School of Microelectronics State Key Laboratory of Integrated Chips and SystemsFudan UniversityShanghai 200433China School of Integrated Circuits Shandong UniversityJinan 250100China National Integrated Circuit Innovation Center Shanghai 201203China School of Electronic Science and Engineering Nanjing UniversityNanjing 210023China Jiashan Fudan Institute Jiashan 314102China

Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InGaZnO-based photoelectric memristor. Under both electrical and optical stimulation, the device successfully emulated synaptic characteristics including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD). Furthermore, we demonstrated the practical application of our synaptic devices through the recognition of handwritten digits. The devices have successfully shown their ability to modulate synaptic weights effectively through light pulse stimulation, resulting in a recognition accuracy of up to 93.4%. The results illustrated the potential of IGZO-based memristors in neuromorphic computing, particularly their ability to simulate synaptic functionalities and contribute to image recognition tasks.

关键词： InGaZnO artificial synapse neuromorphic computing photoelectric memristor

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