In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV *** this study,a novel...
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In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV *** this study,a novel hollow tungsten TSV(W-TSV)is presented and *** hollow structure provides space for the release of thermal *** results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 *** ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability *** average resistance of the TSV was 1.21 *** leakage current was 643 pA and the breakdown voltage was greater than 100 *** resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV *** results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive...
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Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.
Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-freque...
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Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.
Meshing of conventional printed circuit board (PCB) grounds refers to a process in which certain ground planes appear as copper lattices;regular openings are placed at regular intervals. The need for ground meshing fo...
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Within the electronic design automation(EDA) domain, artificial intelligence(AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutio...
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Within the electronic design automation(EDA) domain, artificial intelligence(AI)-driven solutions have emerged as formidable tools, yet they typically augment rather than redefine existing methodologies. These solutions often repurpose deep learning models from other domains, such as vision, text, and graph analytics, applying them to circuit design without tailoring to the unique complexities of electronic circuits. Such an “AI4EDA” approach falls short of achieving a holistic design synthesis and understanding,overlooking the intricate interplay of electrical, logical, and physical facets of circuit data. This study argues for a paradigm shift from AI4EDA towards AI-rooted EDA from the ground up, integrating AI at the core of the design process. Pivotal to this vision is the development of a multimodal circuit representation learning technique, poised to provide a comprehensive understanding by harmonizing and extracting insights from varied data sources, such as functional specifications, register-transfer level(RTL) designs, circuit netlists,and physical layouts. We champion the creation of large circuit models(LCMs) that are inherently multimodal, crafted to decode and express the rich semantics and structures of circuit data, thus fostering more resilient, efficient, and inventive design methodologies. Embracing this AI-rooted philosophy, we foresee a trajectory that transcends the current innovation plateau in EDA, igniting a profound “shift-left” in electronic design methodology. The envisioned advancements herald not just an evolution of existing EDA tools but a revolution, giving rise to novel instruments of design-tools that promise to radically enhance design productivity and inaugurate a new epoch where the optimization of circuit performance, power, and area(PPA) is achieved not incrementally, but through leaps that redefine the benchmarks of electronic systems' capabilities.
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing a...
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The contradiction between the high number of visually handicapped people and the scarcity of guide dogs has stimulated the demand for electronic guide dogs(EGDs).Here,we demonstrate an EGD by leveraging piezoresistors...
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The contradiction between the high number of visually handicapped people and the scarcity of guide dogs has stimulated the demand for electronic guide dogs(EGDs).Here,we demonstrate an EGD by leveraging piezoresistors on a MoS_(2)/Ge heterostructure for simultaneous pressure-sensing and optical-sensing *** device has excellent gating capability and exhibits large positive and negative photoresponses under visible(532 nm,182 A/W)and infrared(1550 nm,37 A/W)*** characteristics allow the device to efficiently classify different obstacles at all times of day using pressure and light *** device reaches nearly 100%accuracy after 48 training sessions when used to classify frequent *** device adopts passive and active detection modes during the day and night,respectively,which improves the battery life of the *** work provides a significant reference for the future design of EGDs,which may help a greater number of visually impaired people by reducing the cost of such devices.
Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InG...
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Photoelectric synaptic devices could emulate synaptic behaviors utilizing photoelectric effects and offer promising prospects with their high-speed operation and low crosstalk. In this study, we introduced a novel InGaZnO-based photoelectric memristor. Under both electrical and optical stimulation, the device successfully emulated synaptic characteristics including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), long-term potentiation (LTP), and long-term depression (LTD). Furthermore, we demonstrated the practical application of our synaptic devices through the recognition of handwritten digits. The devices have successfully shown their ability to modulate synaptic weights effectively through light pulse stimulation, resulting in a recognition accuracy of up to 93.4%. The results illustrated the potential of IGZO-based memristors in neuromorphic computing, particularly their ability to simulate synaptic functionalities and contribute to image recognition tasks.
The synthesizable and parameterizable RISC-V microarchitecture, combined with multi-objective optimization-based Design Space Exploration (DSE), facilitates agile adaptation to various microprocessor designs for custo...
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This paper presents a 74.8-88.8 GHz low-noise amplifier (LNA) in a 55-nm CMOS technology. The LNA employs one common-gate (CG) stage, one common-source (CS) stage, and two cascode stages. A hybrid broadband interstage...
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