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IEEE International Symposium on circuits and systems (ISCAS)

作者： K. Waheed F.M. Salam Circuits Systems and Artificial Neural Networks Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

The paper discusses state space blind source recovery (BSR) for minimum phase and non-minimum phase mixtures of Gaussian and non-Gaussian distributions. The state space natural gradient approach results in compact iterative update laws for BSR. Two separate state space algorithms for minimum phase and non-minimum phase mixing environments are presented. The advantages and disadvantages of both algorithms in the context of multiple source distribution mixtures are examined. The presented BSR algorithms require use of nonlinearities, which depend on the distribution of the unknown sources. We propose use of an adaptive nonlinearity based on the batch kurtosis of the output. This renders the adaptive estimation of the demixing network completely blind.

关键词： state-space methods Signal processing algorithms Iterative algorithms Gaussian distribution circuits Artificial neural networks Laboratories Iterative methods Adaptive estimation Adaptive signal processing

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Statistical process control for solder deposition and yield enhancement

Statistical process control for solder deposition and yield ...

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Electronics Packaging Technology Conference (EPTC)

作者： R. Muthaiyan V. Barba K. Srihari Department of Systems Science and Industrial Engineering State University of New York Binghamton NY USA IBM Microelectronics Endicott Interconnect Technologies Inc. Endicott NY USA

In a generic surface mount printed circuit board assembly line, the largest segment of process-related defects can be ascribed to the solder paste deposition process. The amount of solder paste that is deposited significantly affects both process yields and product reliability. In order to monitor the solder deposition process, surface mount printed circuit board assembly incorporates vision systems with 3D paste inspection capability. But the possibility of capturing both data and the resulting knowledge that represents fluctuations in production mix and volume (to ensure effective continuous real-time monitoring) becomes infeasible because (i) inspection data is not archived and (ii) the inspection tools are not combined with active statistical process control. Having an information systems solution to access and retrieve the historical data from the inspection stations and perform statistical analysis on the available data set would aid continuous monitoring/improvement of the process. This paper provides an insight into the importance of historical data and a software model ('Cyberstat Advisor') that facilitates statistical process control (SPC) and data analysis in the solder deposition process. In order to assist process improvement, data generated by the solder deposition inspection machine was converted and mapped into a relational database format. The 'Cyberstat Advisor' retrieves and utilizes the information from this database. This tool uses heuristics to search and sift through the extensive database. Based on historical data, the 'CyberStat Advisor' can (i) calculate the control limits for a site in the Printed Circuit Boards (PCBs) that had been inspected and (ii) compute the process capability of the solder paste printer with respect to a particular site. This module can also plot run charts, range charts, and bar charts for any site. These visual representations help to better understand the process, facilitating in process improvement.

关键词： Process control Inspection Printed circuits Monitoring Relational databases Information retrieval Assembly systems Machine vision Fluctuations Continuous production

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A mixed mode neuro-VLSI chip for high speed applications

A mixed mode neuro-VLSI chip for high speed applications

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Midwest Symposium on circuits and systems (MWSCAS)

作者： K. Waheed F.M. Salam Circuits Systems And Neural Networks Laboratory Department of Electrical and Computer Engineering Michigan State University East Lansing MI USA

ISBN: (纸本)078037150X

This paper presents selected design and operation details of a custom integrated neural chip. This neural processing chip is designed in the recent 0.18 /spl mu/m, single poly, six-layer Cu interconnect technology. The chip realizes an architecture that achieves the task of autonomous-learning execution times in micro to milli seconds. The core consists of basic building blocks of 4-quadrant multipliers, transconductance amplifiers, and active load resistances, for analog (forward) network processing and learning modules. Super-imposed on the processing network are digital memory and control modules composed of D-Flipflops, ADC, Multiplying D/A Converter (MDAC), decoders, multiplexers and comparators for parameter (weight) storage, logical control and analog/digital conversions.

关键词： Copper Integrated circuit interconnections Very large scale integration Neural networks Process design LAN interconnection Communication system control Testing Application software Laboratories

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Parametric studies of the thermal performance of a Tape Ball Grid Array (TBGA) package

Parametric studies of the thermal performance of a Tape Ball...

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ASME 2000 International Mechanical engineering Congress and Exposition, IMECE 2000

作者： Tonapi, Sandeep S. Sathe, Sanjeev B. Srihari, K. Sammakia, Bahgat B. Department of Systems Science and Industrial Engineering State University of New York at Binghamton BinghamtonNY13902-6000 United States Microelectronics Division IBM Corporation EndicottNY13760 United States Department of Systems Science and Industrial Engineering State University of New York BinghamtonNY13902-6000 United States Department of Mechanical Engineering State University of New York BinghamtonNY13902-6000 United States

ISBN: (纸本)9780791819166

This paper deals with parametric studies to evaluate the thermal performance of a Tape Ball Grid Array (TBGA) package. A cover plate is attached to the back side of the chip to enhance heat transfer from the module. The package is attached to an organic carrier and placed in a vertical channel. A conjugate heat transfer model is used accounting for conduction in the package and the card and convection in the surrounding air. The effect of location of the TBGA on a card with 0, 1 and 2 power planes is evaluated for thermal performance. Five different locations of the TBGA on the card are investigated. Heat dissipation is studied for forced convection (2, 1, and 0.5m/s). No significant difference in chip junction temperatures for the different locations is observed. Temperature distribution along the card centerline and the module centerline are used to discuss the physical phenomenon that is occurring. Copyright © 2000 by ASME.

关键词： Ball grid arrays

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Integration of environment into product design and manufacturing: theory and implementation

Integration of environment into product design and manufactu...

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IEEE International Conference on systems, Man and Cybernetics

作者： R. Lal Tummala Y. Chun S. Melnyk R. Calantone Department of Electrical and Computer Engineering Integrated Circuits and Systems Group USA Department of Marketing and Supply Chain Management Michigan State University USA

The design of environmentally conscious manufacturing (ECM) systems requires quantitative tools to study the impact of the alternative technologies, schedulers, materials and designs used. Such a computer-based tool was developed at the authors' university. This is based on process network theory, also developed at the authors' university. It provides a systematic framework by mapping the physical part of the manufacturing system as a network of transformation, transport and recycling processes. This paper reviews the theory and discusses its computer implementation. To facilitate the user community (managers and designers of different backgrounds), this tool was developed with an easy-to-use graphical interface under the Linux operating system. A Java version has also been implemented for universal availability on the Internet.

关键词： Product design Electrochemical machining Job shop scheduling Processor scheduling Network theory (graphs) Manufacturing systems Recycling Linux Operating systems Java

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A neuro-chip for real-time learning, processing and control

A neuro-chip for real-time learning, processing and control

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IEEE International Symposium on circuits and systems (ISCAS)

作者： F.M. Salam Circuits Systems and Artificial Neural Networks Laboratory Department of Electrical Engineering Michigan State University East Lansing MI USA

We present results of several experiments of a neural network with temporal learning on a single chip. The single chip configuration is a 2-D scalable array with learning constructed via simple modular CMOS building blocks. We report on learning prototype periodic temporal signals which may be displayed as a closed curve, a figure-8 shape, or an arbitrary periodic or aperiodic shapes in the state space. The experiments demonstrate the instantaneous learning by the chip of these shapes.

关键词： Process control Neurons Testing Shape Frequency Displays Recurrent neural networks Differential equations Time measurement Limit-cycles

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A 1.8 V 900 MHz CMOS RF receiver

A 1.8 V 900 MHz CMOS RF receiver

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IEEE Asia-Pacific Conference on circuits and systems

作者： S. Wang R. Sheen O.T.-C. Chen Kuang-Chung Tao Signal and Media Laboratories Department o Electrical Engineering National Chung Cheng University Chiayi Taiwan High Frequency Circuits Design Department Microelectronics Systems Design Tech. Division Industrial Technology and Research Institute Hsinchu Taiwan

A 1.8 V 900 MHz CMOS RF receiver which integrates a low-noise amplifier, two down-conversion mixers, and a local oscillator has been developed. In this receiver, the single-ended two-stage low-noise amplifier is realized with a power gain of 11.6 dB and a noise figure of 3.8 dB at 900 MHz. Its 1 dB compression point is around -9 dBm. The down-conversion mixer with a single-ended RF input is designed with a conversion gain of -4 dB and the 1 dB compression point of -6 dBm. The local oscillator is implemented by using a phased-locked loop which can provide stable high-frequency oscillation signals. The proposed RF receiver was fabricated by using TSMC 0.6 /spl mu/m single-poly-triple-metal CMOS technology with a die size of 2.4 mm/spl times/1.8 mm.

关键词： Radio frequency Low-noise amplifiers RF signals Impedance Circuit noise Radiofrequency amplifiers Local oscillators CMOS technology Gain Integrated circuit technology

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Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures

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Journal of VLSI Signal Processing systems for Signal, Image, and Video Technology 1998年第1期18卷 51-64页

作者： Bierens, Laurens Deprettere, Ed TNO Phys. and Electronics Laboratory 2509 JG The Hague P.O.Box 96864 Netherlands Delft Univ. of Technology Dept. of Electrical Engineering 2600 GA Delft P.O.Box 5031 Netherlands Delft University of Technology Delft Netherlands TNO Phys. and Electronics Laboratory The Hague Netherlands Ghent State University Ghent Belgium Department of Electrical Engineering Circuits and Systems Section Signal Processing Group Netherlands Philips Research Eindhoven Netherlands

We present an efficient approach for the partitioning of algorithms implementing long convolutions. The dependence graph (DG) of a convolution algorithm is locally sequential globally parallel (LSGP) partitioned into smaller, less complex convolution algorithms. The LSGP partitioned DG is mapped onto a signal flow graph (SFG), in which each processor element (PE) performs a small convolution algorithm. The key is then to reduce the complexity of the SFG in two steps: 1. local reduction of complexity: the short Fast Fourier Transform (FFT) is used to perform the small convolution within the PE, 2. global reduction of complexity: the short FFTs within the PEs are relocated to the global level, where redundant short FFT operations are eliminated. The remaining operation within the PEs is now a simple element-wise multiply-add. After a graph transform, the structure of the SFG kernel is recognized as a set of parallel small convolutions. If we use the short FFT to perform these short convolutions, we come to our final realization of the long convolution algorithm. The computational complexity of this realization is close to the optimum for convolutions, that is, script O sign (N log N). Our approach is thus achieving this N log N - low without having to implement large-size FFTs. We use, instead, small FFT blocks. The advantage is that small FFT transforms are commercially available, and that they can even be implemented in single-chip VLSI architectures. Our final SFG is three dimensional and can be mapped efficiently onto prototype architectures or dedicated VLSI processors. We demonstrate the procedure in the paper by a design example: the implementation of a prototype convolution architecture that we designed for a real-time radar imaging system.

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Silicon-on-Insulator 2×2 Symmetric Optical Switch Based on Total Internal Reflection

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Chinese Physics Letters 1997年第2期14卷 106-108页

作者： ZHAO Ce-zhou LIU En-ke LI Guo-zheng LIU Yu-liang GUO Lin Microelectronics Institute Xidian UniversityXi'an 710071 Department of Electronic Engineering Xi'an Jiaotong UniversityXi'an 710049 Sichuan Institute of Solid-state Circuits Chongqing 630060

Based on the large cross-section single-mode rib waveguide condition,the total internal reflection and the free-carrier plasma dispersion effect,a silicon-on-insulator(SOI)2×2 symmetric optical waveguide switch with a transverse injection structure has been proposed and fabricated,in which the SOI technique utilizes silicon and silicon dioxide thermal bonding and *** device performance is measured at the wavelength of 1.3μ*** shows that the crosstalk and insertion loss are less than -18.1 and 4.8 dB,respectively,at an injection current of 60mA,and response time is 110 ns.

关键词： waveguide SOI polishing

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A neuro-chip with temporal learning: test results for signal/shape generation

A neuro-chip with temporal learning: test results for signal...

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Asilomar Conference on Signals, systems & Computers

作者： F.M. Salam Circuits Systems and Artificial Neural Networks Laboratory Department of Electrical Engineering Michigan State University East Lansing MI USA

We briefly describe a recently designed neural network with temporal learning. The developed learning rule extends the temporal learning to realize a forward instantaneous update scheme, suitable for complete analog hardware implementation. The single chip configuration is a two-dimensional scalable array with learning constructed via simple scalable CMOS building blocks. We report on extensive test results of learning prototype periodic temporal signals which may be displayed as a closed curve or a figure-8 shape in the state space. Several experimental tests demonstrating the instantaneous learning by the chip of these shapes are reported.

关键词： Testing Shape Signal generators Recurrent neural networks Artificial neural networks Hardware Signal processing algorithms state-space methods Signal processing Control systems

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