We present a model for recurrent artificial neural networks which can store any number of any pre-specified patterns as energy local minima. Therefore, all the pre-specified patterns can be stored and retrieved. We su...
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This paper describes a CMOS comparator which uses a novel feedforward autozeroing circuitry to obtain high speed and low threshold uncertainty. Fabricated in a standard 2μm digital CMOS process, it achieved an input ...
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We describe various analog chips with digital on-chip learning capability. A system of four neural chips has been constructed. The chips and the system have passed the testing stage and have been utilized in various e...
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The authors present a model for recurrent artificial neural networks which can store any number of any prespecified patterns as energy local minima. Therefore, all the prespecified patterns can be stored and retrieved...
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The authors present a model for recurrent artificial neural networks which can store any number of any prespecified patterns as energy local minima. Therefore, all the prespecified patterns can be stored and retrieved. The authors summarize the model's stability properties. They then give two examples, showing how this model can be used in image recognition and association.< >
Various analog chips with digital on-chip learning capability are described. A system of four neural chips has been constructed. The chips and the system have passed the testing stage and have been utilized in various...
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Various analog chips with digital on-chip learning capability are described. A system of four neural chips has been constructed. The chips and the system have passed the testing stage and have been utilized in various experiments in image processing, recognition, and association. A prototype system consisting of four chips has 289 neurons and can process sub-images of 17*17 resolution in less than 400 ns. Second generation designs of ANNs using the dendro-dendritic ANN (DANN) architecture and the usual feedback (Hopfield-type) architecture are discussed, and transient behavior measurement that confirms that the worst convergence time to the desired steady state in less than 400 ns are presented.< >
The through-line (TL) method is introduced to replace the through-reflect-line (TRL) deembedding procedure. TL utilizes measurements of two lengths of line following approximate open-short-line calibration. TL account...
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The through-line (TL) method is introduced to replace the through-reflect-line (TRL) deembedding procedure. TL utilizes measurements of two lengths of line following approximate open-short-line calibration. TL accounts for the frequency-dependent characteristic impedance of the line and avoids the periodic glitches inherent in the TRL procedure.< >
All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employin...
All-MOS analog vector-vector multipliers are described and designed for the implementation of the linear multiplication between analog signals and analog synaptic weights in artificial neural networks (ANNs). Employing these multipliers, large-scale artificial neural networks can be implemented using fewer MOS transistors than are required by implementations employing the so-called Gilbert multiplier. PSPICE circuit simulations have been extensively executed in order to quantify the performance of these multipliers by measuring the following specifications: maximum percentage error, output offset, X or Y nonlinearity, X or Y feedthrough, small-signal bandwidth, and slew rate. An 11-dimensional analog vector multiplier has been designed on a 40-pin MOSIS TINYCHIP with analog pads using the MAGIC VLSI tools and has been fabricated using 2 μm CMOS n-well process via MOSIS.
The Z-J algorithm given by A.J. Viterbi (1967) and K. Zigangirov (1966) is a bit-error correcting algorithm for long constraint length convolutional codes. The feasibility of implementing the algorithm in a single VLS...
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The Z-J algorithm given by A.J. Viterbi (1967) and K. Zigangirov (1966) is a bit-error correcting algorithm for long constraint length convolutional codes. The feasibility of implementing the algorithm in a single VLSI chip to obtain bit error correction for systems with input data rates approaching on-chip clock rates, which currently range up to hundreds of megabits/s, is described. Simulations of the algorithm under VLSI constraints demonstrate potential error correction performance superior to available maximum likelihood decoders, which operate at shorter constraint length, at noise levels below decoding limits for sequential decoders. Stack dimensions required to achieve the result are on the order of 250*100 bits.< >
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