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2023 International Symposium on Electromagnetic Compatibility - EMC Europe, EMC Europe 2023

作者： Shivdeep Sharma, Sahil Boyapati, Subrahmanyam Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Carinthia University of Applied Sciences Integrated Systems and Circuit Design Group Carinthia Austria

ISBN: (纸本)9798350324006

Electromagnetic Interference (EMI) at the input of an Operational Transconductance Amplifier (OTA) leads to a DC offset voltage at the output. The amount of EMI-induced offset depends on the frequency and amplitude of the interferer signal. Various phenomena are dominant at different frequencies, such as the asymmetric slew rate is responsible for offset induced at frequencies around the Unity Gain Frequency (UGF). This paper identifies the causes and presents a design approach to optimize the slew rate and reduce the output offset without using overhead area and power. Channel length modulation of the tail current source transistor and its reduced impedance is due to the effective capacitance (CT) at the tail node becoming the culprit and adding more asymmetry to the slew rate. This is addressed using the cascode tail current source and additional gate-to-source capacitance Cgsx. Two-stage Miller OTA is designed in the standard 0.18 μm CMOS technology. Monte Carlo and the post-layout simulation results are presented to consider the parasitics, process variations, and mismatch effects. © 2023 IEEE.

关键词： Operational amplifiers

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Data-Filtered Prediction with Decomposition and Amplitude-Aware Permutation Entropy for Workload and Resource Utilization in Cloud Data Centers

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IEEE Internet of Things Journal 2025年第12期12卷 19189-19201页

作者： Yuan, Haitao Hu, Qinglong Wang, Meijia Wang, Shen Bi, Jing Buyya, Rajkumar Shi, Shuyuan Yang, Jinhong Zhang, Jia Zhou, MengChu Beihang University School of Automation Science and Electrical Engineering Beijing100191 China City University of Hong Kong Department of Computer Science Hong Kong999077 Hong Kong Beijing University of Technology School of Software Engineering The Faculty of Information Technology Beijing100124 China Lab School of Computing and Information Systems MelbourneVIC3010 Australia Beihang University School of Integrated Circuit Science and Engineering Beijing China CSSC Systems Engineering Research Institute Beijing China Southern Methodist University Department of Computer Science The Lyle School of Engineering DallasTX75205 United States New Jersey Institute of Technology Department of Electrical and Computer Engineering NewarkNJ07102 United States

In recent years, cloud computing has witnessed widespread applications across numerous organizations. Predicting workload and computing resource data can facilitate proactive service operation management, leading to substantial improvements in quality of service and cost efficiency. However, these data often exhibit non-linearity, high volatility, and interdependencies across different categories, presenting challenges for accurate forecasting. Consequently, there is a critical need to develop a method that thoroughly and comprehensively analyzes all available data to forecast future trends effectively. This work proposes a novel integrated data-enhanced prediction model named SVAPI for achieving high-accuracy workload prediction in cloud computing systems. SVAPI employs the Savitzky-Golay filter, Variational mode decomposition, and the mode selection based on Amplitude-aware Permutation entropy for feature processing, whose features are subsequently utilized by Informer for multivariate joint analysis of the enhanced data, achieving high-precision prediction. Ablation and comparative experiments with advanced prediction models are conducted on the Google cluster trace and other typical datasets. Realistic data-driven results indicate that SVAPI improves the prediction accuracy by 37.7% compared to the original Informer, with each module contributing to the performance enhancement. Furthermore, compared with Autoformer, SVAPI enhances the prediction accuracy of workload, CPU, and memory by 65.6%, 66.9%, and 70.8%, respectively, demonstrating that SVAPI owns strong abilities in noise filtering, feature processing, and multivariate joint analysis for achieving higher prediction accuracy. © 2014 IEEE.

关键词： Quality of service

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A Self-Calibration Logic circuit Agnostic to Offset Calibration Technique for High-Precision Dynamic Comparator 4

A Self-Calibration Logic Circuit Agnostic to Offset Calibrat...

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4th IEEE Women in technology Conference, WINTECHCON 2023

作者： Sharma, Nidhi Srivastava, Rajesh K. Hande, Vinayak Sehgal, Deep Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Semi-conductor Laboratory S.A.S Nagar India Carinthia University of Applied Sciences Integrated Systems and Circuit Design Villach Austria

ISBN: (纸本)9798350300567

This paper proposes a calibration technique agnostic calibration logic circuitry for the self-calibration of the high-precision dynamic comparator, which can be used in major self-calibration techniques to activate the calibration and offset polarity change detection for completion of the calibration. This paper also briefly reviews the different comparator offset cancellation techniques, i.e., auto-zeroing, self-calibration, and chopper stabilization. The proposed calibration logic is implemented in a dynamic comparator's effective trans-conductance controlled offset calibration in SCL 180 nm technology. The standard deviation of the input-referred offset of the comparator is reduced to 445 μV from 2.85 mV with a complete calibration range of 5σ offset, therefore qualifying it for high-speed flash ADCs and asynchronous SAR ADCs. The power consumption at 1 GHz operating frequency is 154.6 μW. © 2023 IEEE.

关键词： Calibration

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In-Memory Neural Stochastic Differential Equations with Probabilistic Differential Pair Achieved by In-situ P-bit using CMOS Integrated Voltage-Controlled Magnetic Tunnel Junctions

In-Memory Neural Stochastic Differential Equations with Prob...

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2024 IEEE International Electron Devices Meeting, IEDM 2024

作者： Xiao, Zhihua Hou, Yaoru Tong, Zihan Jiang, Yicheng Zhang, Yiyang Wu, Xuezhao Lee, Albert Wu, Di Cai, Hao Shao, Qiming Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Department of Physics The Hong Kong University of Science and Technology Hong Kong InstonTech Suzhou China School of Integrated Circuit Southeast University Nanjing China

ISBN: (纸本)9798350365429

The probabilistic bit (P-bit) is the core of probabilistic computing. We propose a novel in-situ P-bit compatible with compute-in-memory (CIM) schemes using voltage-controlled magnetic tunnel junctions (MTJs) to eliminate the generation-sample-transfer-compute paradigm of current P-bits. The conventional approach of sampling and transferring random sequences between separate P-bits and computing units reintroduces the memory bottleneck seen in von Neumann architectures, thereby limiting the efficiency of probabilistic computing. By pairing a data-bit and a P-bit as a probabilistic differential pair in a crossbar array, we enable random sequences to be directly utilized for computing. This generation-compute scheme eradicates the sampling and transfer costs associated with previous probabilistic computing methods. Full reuse of devices in the differential cells allows for probabilistic CIM with a large number of P-bits and high parallelism, suitable for real-world probabilistic computing tasks. We demonstrated in-memory neural stochastic differential equations for the reverse diffusion process in generative models. The results shows that without the bottlenecks, in-situ P-bit throughput is 6×faster and 2.19×more efficient than ex-situ P-bits using the same technology. Compared to other devices and schemes, the proposed scheme is 3×faster than state-of-the-art CMOS designs and 1.36×more energy efficient. © 2024 IEEE.

关键词： CMOS integrated circuits

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6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction 8

6-bit 1-GS/s Partially Active Flash ADC with Comparator Offs...

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8th IEEE International Symposium on Smart Electronic systems, iSES 2022

作者： Sharma, Nidhi Hande, Vinayak Srivastava, Rajesh Kumar Das, Devarshi Mrinal Indian Institute of Technology Ropar Department of Electrical Engineering Rupnagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria Semi-conductor Laboratory S.A.S Nagar India

ISBN: (纸本)9798350399226

This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW. © 2022 IEEE.

关键词： Comparators (optical)

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Lifecycle Management of Emerging Memories

Lifecycle Management of Emerging Memories

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IEEE European Test Symposium (ETS)

作者： Moritz Fieback Letícia Maria Bolzani Pöhls QCE Department Faculty EEMCS Delft University of Technology The Netherlands Group of Test & Reliability of Emerging Applications Chair of Integrated Digital Systems and Circuit Design RWTH Aachen University Germany

ISBN: (数字)9798350349320

ISBN: (纸本)9798350349337

Traditional charge-based memories such as dynamic RAM (DRAM) and flash are facing more and more manufacturing, reliability, energy, and speed issues. A growing group of emerging memory technologies, such resistive RAM (RRAM), spin-transfer torque magnetic RAM (STT-MRAM), phase change memory (PCM), and Ferroelectric (Fe) devices (e.g., FeFET, FeRAM), address these problems. Nonetheless, these technologies are also not perfect, and thus special care must be taken to ensure that the lifecycle management, from design to obsolescence, of these memories is as optimal as possible. Lifecycle management is being developed for traditional technologies, but these are not optimized for emerging memories yet. In this paper, we present the first steps of lifecycle management for emerging memories. We analyze the different lifecycle phases that exist for two case studies on RRAM and FeFET-based memories. In this analysis, we identify how the phases affect each other and which optimizations are possible by analyzing the complete lifecycle. Finally, we compare the lifecycle phases of these two emerging memories to see how a unified approach can be developed.

关键词： Phase change materials Torque Nonvolatile memory Memory management Resistive RAM Random access memory Phase change memory

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A figure of merit for noise power and area optimization of neural amplifiers

TechRxiv

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TechRxiv 2023年

作者： Sharma, Sahil Hande, Vinayak Gopal Das, Devarshi Mrinal Department of Electrical Engineering Indian Institute of Technology Ropar Roopnagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

Neural amplifiers are desired to have low power, low noise, low area, high input impedance, high pass response and high CMRR. Widely used topologies like capacitvely coupled instrumentaion amplifiers, capacitvely couled chopper instrumentaion amplifier and current feedback instrumentations amplifer offer different features and drawbacks. The noise power optimization of an amplifier can be measured using noise efficiency factor(NEF). We propose a figure of merit, Noise and area efficiency factor(NAEF) which captures the noise and area optimization of the amplifier. One more figure of merit which is the product of NEF and NAEF captures the noise power and area optimization of an amplifier. © 2023, CC BY.

关键词： Efficiency

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A Two Stage Miller OpAmp with Low Voltage Cascode Current Source with High EMI Immunity

A Two Stage Miller OpAmp with Low Voltage Cascode Current So...

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IEEE International Symposium on Electromagnetic Compatibility - EMC Europe

作者： Shivdeep Sahil Sharma Subrahmanyam Boyapati Devarshi Mrinal Das Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar India Integrated Systems and Circuit Design Group Carinthia University of Applied Sciences Carinthia Austria

Electromagnetic Interference (EMI) at the input of an Operational Transconductance Amplifier (OTA) leads to a DC offset voltage at the output. The amount of EMI-induced offset depends on the frequency and amplitude of the interferer signal. Various phenomena are dominant at different frequencies, such as the asymmetric slew rate is responsible for offset induced at frequencies around the Unity Gain Frequency (UGF). This paper identifies the causes and presents a design approach to optimize the slew rate and reduce the output offset without using overhead area and power. Channel length modulation of the tail current source transistor and its reduced impedance is due to the effective capacitance (C T ) at the tail node becoming the culprit and adding more asymmetry to the slew rate. This is addressed using the cascode tail current source and additional gate-to-source capacitance C gsx . Two-stage Miller OTA is designed in the standard 0.18 μm CMOS technology. Monte Carlo and the post-layout simulation results are presented to consider the parasitics, process variations, and mismatch effects.

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A Self-Calibration Logic circuit Agnostic To Offset Calibration Technique For High-Precision Dynamic Comparator

A Self-Calibration Logic Circuit Agnostic To Offset Calibrat...

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Women in technology Conference (WINTECHCON), 2022 IEEE

作者： Nidhi Sharma Rajesh K. Srivastava Vinayak Hande Deep Sehgal Devarshi Mrinal Das Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar India Semi-conductor Laboratory Ministry of Electronics & Information Technology (MeitY) S.A.S Nagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

This paper proposes a calibration technique agnostic calibration logic circuitry for the self-calibration of the high-precision dynamic comparator, which can be used in major self-calibration techniques to activate the calibration and offset polarity change detection for completion of the calibration. This paper also briefly reviews the different comparator offset cancellation techniques, i.e., auto-zeroing, self-calibration, and chopper stabilization. The proposed calibration logic is implemented in a dynamic comparator’s effective trans-conductance controlled offset calibration in SCL 180 nm technology. The standard deviation of the input-referred offset of the comparator is reduced to 445 μV from 2.85 mV with a complete calibration range of 5σ offset, therefore qualifying it for high-speed flash ADCs and asynchronous SAR ADCs. The power consumption at 1 GHz operating frequency is 154.6 μW.

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A Rapid Adaptation Approach for Dynamic Air‑Writing Recognition Using Wearable Wristbands with Self‑Supervised Contrastive Learning

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Nano-Micro Letters 2025年第2期17卷 417-431页

作者： Yunjian Guo Kunpeng Li Wei Yue Nam‑Young Kim Yang Li Guozhen Shen Jong‑Chul Lee Department of Electronic Convergence Engineering Kwangwoon UniversitySeoul 01897South Korea Radio Frequency Integrated Circuit(RFIC)Bio Centre Kwangwoon UniversitySeoul 01897South Korea Department of Electronic Engineering Kwangwoon UniversitySeoul 01897South Korea School of Microelectronics Shandong UniversityJinan 250101People’s Republic of China State Key Laboratory of Integrated Chips and Systems Fudan UniversityShanghai 200433People’s Republic of China School of Integrated Circuits and Electronics Beijing Institute of TechnologyBeijing 100081People’s Republic of China

Wearable wristband systems leverage deep learning to revolutionize hand gesture recognition in daily *** existing approaches that often focus on static gestures and require extensive labeled data,the proposed wearable wristband with selfsupervised contrastive learning excels at dynamic motion tracking and adapts rapidly across multiple *** features a four-channel sensing array composed of an ionic hydrogel with hierarchical microcone structures and ultrathin flexible electrodes,resulting in high-sensitivity capacitance *** wireless transmission from a Wi-Fi module,the proposed algorithm learns latent features from the unlabeled signals of random wrist ***,only few-shot labeled data are sufficient for fine-tuning the model,enabling rapid adaptation to various *** system achieves a high accuracy of 94.9%in different scenarios,including the prediction of eight-direction commands,and air-writing of all numbers and *** proposed method facilitates smooth transitions between multiple tasks without the need for modifying the structure or undergoing extensive task-specific *** utility has been further extended to enhance human–machine interaction over digital platforms,such as game controls,calculators,and three-language login systems,offering users a natural and intuitive way of communication.

关键词： Wearable wristband Self-supervised contrastive learning Dynamic gesture Air-writing Human-machine interaction

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