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In-Memory Neural Stochastic Differential Equations with Probabilistic Differential Pair Achieved by In-Situ P-Bit Using CMOS Integrated Voltage-Controlled Magnetic Tunnel Junctions

In-Memory Neural Stochastic Differential Equations with Prob...

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International Electron Devices Meeting (IEDM)

作者： Zhihua Xiao Yaoru Hou Zihan Tong Yicheng Jiang Yiyang Zhang Xuezhao Wu Albert Lee Di Wu Hao Cai Qiming Shao Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong China AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong China Department of Physics The Hong Kong University of Science and Technology Hong Kong China InstonTech Suzhou China School of Integrated Circuit Southeast University Nanjing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

The probabilistic bit (P-bit) is the core of probabilistic computing. We propose a novel in-situ P-bit compatible with compute-in-memory (CIM) schemes using voltage-controlled magnetic tunnel junctions (MTJs) to eliminate the generation-sample-transfer-compute paradigm of current P-bits. The conventional approach of sampling and transferring random sequences between separate P-bits and computing units reintroduces the memory bottleneck seen in von Neumann architectures, thereby limiting the efficiency of probabilistic computing. By pairing a data-bit and a P-bit as a probabilistic differential pair in a crossbar array, we enable random sequences to be directly utilized for computing. This generation-compute scheme eradicates the sampling and transfer costs associated with previous probabilistic computing methods. Full reuse of devices in the differential cells allows for probabilistic CIM with a large number of P-bits and high parallelism, suitable for real-world probabilistic computing tasks. We demonstrated in-memory neural stochastic differential equations for the reverse diffusion process in generative models. The results shows that without the bottlenecks, in-situ P-bit throughput is $6\times$ faster and $2.19\times$ more efficient than ex-situ P-bits using the same technology. Compared to other devices and schemes, the proposed scheme is $3\times$ faster than state-of-the-art CMOS designs and $1.36\times$ more energy efficient.

关键词： Stochastic processes Differential equations Parallel processing Probabilistic logic In-memory computing Common Information Model (computing) Probabilistic computing Junctions Magnetic tunneling Random sequences

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Wideband Antenna-in-Package Dielectric Resonator Antenna Using High-Resistance Silicon Substrate for Satellite Communications 16

Wideband Antenna-in-Package Dielectric Resonator Antenna Usi...

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16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies, UCMMT 2023

作者： Fang, Ning-Shuang Wang, Qiang Chen, Li-Tao Leung, Kwok Wa Yang, Nan Lu, Kai Su, Guodong Long, Yunliang and Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-sen University Guangzhou510006 China Limited China State Key Laboratory of Terahertz and Millimeter Waves and Department of Electronic Engineering City University of Hong Kong Hong Kong SAR China Information and Communication Technology Center CityU Shenzhen Research Institute Shenzhen518057 China Zhejiang Provincial Laboratory of Integrated Circuit Design Hangzhou Dianzi University Hangzhou310018 China

ISBN: (纸本)9798350339406

A wideband antenna-in-package (AiP) dielectric resonator antenna (DRA) is presented in this paper. Air vias and metallic vias are used to form the equivalent DRA. To obtain a wideband design, a slot-loaded DRA mode and a fundamental DRA mode are simultaneously excited. Two metal strips are attached on the top surface for better impedance matching. To verify the design idea, a prototype is designed with a simulated bandwidth larger than 20 %. It should be mentioned that the presented design is compatible with silicon-based process, and thus suitable for AiP and heterogeneous integration systems. © 2023 IEEE.

关键词： Strip metal

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BAG2 Assisted Hierarchical Analog Layout Synthesis for Planar Technologies

BAG2 Assisted Hierarchical Analog Layout Synthesis for Plana...

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Austrian Workshop on Microelectronics (Austrochip)

作者： Matthew Bio Wolfgang Scherr A. S. Agbemenu Santiago Martin Sondón Johannes Sturm Vinayak Hande Josef Ressel Centre for System-on-Chip Design Automation Carinthia Institute for Microelectronics Carinthia University of Applied Sciences Department of Computer Engineering Kwame Nkrumah University of Science and Technology Kumasi Ghana Department of Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continued to be developed targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley analog generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow as well as encourages design re-use due to using parameterized generators which can be scaled as required and this reduces the layout-development time compared to manual hand-made layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65nm and Cadence GPDK 45nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.

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How hyperspectral imaging and artificial intelligence transform Alzheimer's diagnosis

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Spectroscopy Europe 2021年第6期33卷 18-23页

作者： Lemmens, Sophie De Groef, Lies Charle, Wouter Jayapala, Murali Theunis, Jan Moons, Lieve De Boever, Patrick Stalmans, Ingeborg KU Leuven Biomedical Sciences Group Department of Neurosciences Research Group Ophthalmology Herestraat 49 Leuven3000 Belgium University Hospitals UZ Leuven Department of Ophthalmology Herestraat 49 Leuven3000 Belgium Neural Circuit Development and Regeneration Research Group KU Leuven Belgium Hyperspectral Imaging Technology Research Group Imec Belgium Health Unit VITO Belgium Centre of Excellence Microbial Systems Technology University of Antwerp Belgium Centre for Environmental Sciences Hasselt University Belgium

In a recent multidisciplinary study involving 39 patients, the potential of retinal imaging techniques for the diagnosis of Alzheimer's disease was investigated. An easy-to-use hyperspectral snapshot camera - 16 spectral bands between 460 nm and 620 nm with 10nm bandwidth - was used to quantify amyloid accumulation, while optical coherence tomography allowed the thickness of the retinal nerve fibre layer to be assessed. Dedicated image preprocessing and machine learning were instrumental in discriminating between Alzheimer patients and healthy subjects. The best results were obtained when the hyperspectral and OCT data were combined. © 2021 The Authors.

关键词： Diagnosis

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Ferroelectric materials, devices, and chips technologies for advanced computing and memory applications: development and challenges

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Science China(Information Sciences) 2025年第6期 118-173页

作者： Xiao YU Ni ZHONG Yan CHENG Tianjiao XIN Qing LUO Tiancheng GONG Jiezhi CHEN Jixuan WU Ran CHENG Zhiyuan FU Kechao TANG Jin LUO Tianling REN Fei XUE Lin CHEN Tianyu WANG Xueqing LI Xiuyan LI Ping WANG Xinqiang WANG Jie SUN Anquan JIANG Peiyuan DU Bing CHEN Chengji JIN Jiajia CHEN Haoji QIAN Wei MAO Siying ZHENG Huan LIU Haiwen XU Can LIU Zhihao SHEN Xiaoxi LI Bochang LI Zheng-Dong LUO Jiuren ZHOU Yan LIU Yue HAO Genquan HAN Hangzhou Institute of Technology Xidian University Faculty of Integrated Circuits Xidian University Key Laboratory of Polar Materials and Devices(MOE) Department of Electronics East China Normal University State Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences School of Information Science and Engineering Shandong University College of Integrated Circuit Zhejiang University School of Integrated Circuits Southeast University School of Integrated Circuits Peking University School of Integrated Circuits Tsinghua University Center for Quantum Matter School of Physics Zhejiang University School of Microelectronics State Key Laboratory of Integrated Chips and Systems Fudan University Department of Electronic Engineering Tsinghua University National Key Laboratory of Micro and Nano Fabrication Technology and the Department of Micro-Nano Electronics Shanghai Jiao Tong University State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-Optoelectronics School of Physics Peking University Hangzhou Huarui Chip Innovation Technology Co. Ltd.

Hafnium（Hf） oxide-based ferroelectric materials have emerged as a transformative platform for next-generation non-volatile memory and advanced computing technologies. This review comprehensively examines the development, challenges, and applications of HfO2ferroelectrics, emphasizing their CMOS compatibility, scalability, and robust polarization at nanoscale dimensions. Breakthroughs in doping strategies, stress engineering, and VO control have stabilized the metastable orthorhombic phase, enabling high-performance devices such as ferroelectric RAM（FeRAM）, ferroelectric field-effect transistors（FeFETs）, and ferroelectric tunnel junctions（FTJs）. These devices offer ultrafast switching, low power consumption, and multi-level storage, driving innovations in neuromorphic computing, in-memory processing, and cryogenic systems; nonetheless, they face ongoing challenges in reliability, such as fatigue and imprint effects, and scalability at sub-5 nm technology nodes. Emerging frontiers, such as wurtzite-structured nitrides（e.g., AlScN） and antiferroelectric ZrO2-based systems, have garnered significant attention due to their exceptionally high remanent polarization and promising potential for enhanced endurance, respectively. Further addressing the reliability issues of these emerging ferroelectric materials and the challenges associated with large-scale integration processes through interdisciplinary efforts will unlock the full potential of ferroelectric technologies, positioning them as pivotal enablers of post-Moore computing architectures and sustainable AI-driven applications.

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6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction

6-bit 1-GS/s Partially Active Flash ADC with Comparator Offs...

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IEEE International Symposium on Smart Electronic systems (iSES)

作者： Nidhi Sharma Vinayak Hande Rajesh Kumar Srivastava Devarshi Mrinal Das Department of Electrical Engineering Indian Institute of Technology Ropar Rupnagar India Integrated Systems and Circuit Design Carinthia University of Applied Sciences Villach Austria Semi-conductor Laboratory Ministry of Electronics & Information Technology (MeitY) S.A.S Nagar India

ISBN: (纸本)9798350399233

This paper presents a low-power 6-bit 1 GS/s partially active flash analog-to-digital converters (ADC) in 65-nm CMOS technology. A novel comparator offset correction technique is proposed, which does not require additional foreground calibration cycles. The partially active second-stage comparison is employed for power efficiency. A third-stage comparison is introduced for offset correction using fifteen low-offset comparators, out of which two are activated. The 0.5-bit redundancy from the first-stage provides the tolerance to track-and-hold (T/H) buffer settling error for high-speed applications. The simulation results show that the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 36.36 dB and a spurious-free dynamic range (SFDR) of 48.65 dB at a Nyquist frequency of 500 MHz with the power consumption of 13.98 mW.

关键词： Power demand Simulation Termination of employment Dynamic range CMOS technology Distortion Calibration

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Imaging of dendrites and sparse interneuronal networks with 3D random access microscopy

Imaging of dendrites and sparse interneuronal networks with ...

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Optics and the Brain, BRAIN 2023 - Part of Optica Biophotonics Congress: Optics in the Life Sciences 2023

作者： Rózsa, Balázs Szadai, Zoltán Judák, Linda Chiovini, Balázs Juhász, Gábor Ócsai, Katalin Pálfi, Dénes Mezriczky, Zsolt Szalay, Gergely Katona, Gergely Mihály, Anna Szepesi, Áron Mucsi, Zoltán Roska, Botond Pi, Hyun-Jae Chevy, Quentin Albeanu, Florin Kepecs, Adam Laboratory of 3D functional network and dendritic imaging Institute of Experimental Medicine Budapest1083 Hungary Two-photon measurement technology group The Faculty of Information Technology Pázmány Péter University Budapest Hungary Brain Vision Center Budapest Hungary János Szentágothai Doctoral School of Neurosciences Semmelweis University Budapest Hungary Institute of Molecular and Clinical Ophthalmology Basel Basel Switzerland Neural Circuit Laboratories Friedrich Miescher Institute Basel Switzerland Department of Ophthalmology University of Basel Basel Switzerland Cold Spring Harbor Laboratory Cold Spring HarborNY United States Volen Center for Complex Systems Biology Department Brandeis University WalthamMA United States Departments of Neuroscience and Psychiatry Washington University School of Medicine St. LouisMO United States

ISBN: (纸本)9781957171210

Acousto-optical microscopy is a powerful tool to study spare networks and extensive dendritic arborization from the cortex of behaving animals. We used this novel approach for imaging dendrites and somata of sparse interneuron populations in a combination with auditory discrimination and detection tasks. Our results shed light of not yet known subcellular and network mechanisms from multiple brain regions. © 2023 The Author (s).

关键词： Laser scanning Microscopy Scanning microscopy Spatial resolution Three dimensional imaging Three dimensional measurement

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Impact of Space Charge Modulation on Superjunction-LDMOS

Impact of Space Charge Modulation on Superjunction-LDMOS

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2020 International Symposium on VLSI technology, systems and Applications, VLSI-TSA 2020

作者： Mishra, Aakanksha Kumar, B. Sampath Somayaji, Jhnanesh Shrivastava, Mayank Gupta, Ankur Centre for Applied Research in Electronics Indian Institute of Technology Delhi India Advanced Nanoelectronic Device Circuit Research Group Department of Electronic Systems Engineering Indian Institute of Science Karnataka India

ISBN: (数字)9781728142326

ISBN: (纸本)9781728142326

In this paper, we present the impact of Superjunction (SJ) implant on the performance challenges encountered by LDMOS in the ONstate while developing insights into Space Charge Modulation (SCM) and Quasi-Saturation (QS) behavior in these devices. SJ-device is reported to have four times higher breakdown voltage than the conventional LDMOS device which proves to be an outstanding candidate for switching applications. This paper elucidates the design guidelines for SJ-devices in order to maximize the ON-state performance by mitigating SCM and QS effects while keeping in mind the OFF-state breakdown requirements. © 2020 IEEE.

关键词： Modulation

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Wideband Antenna-in-Package Dielectric Resonator Antenna Using High-Resistance Silicon Substrate for Satellite Communications

Wideband Antenna-in-Package Dielectric Resonator Antenna Usi...

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UK, Europe, China Millimeter Waves and THz technology Workshop (UCMMT)

作者： Ning-Shuang Fang Qiang Wang Li-Tao Chen Kwok Wa Leung Nan Yang Kai Lu Guodong Su Yunliang Long School of Electronics and Information Technology (School of Microelectronics) and Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems Sun Yat-Sen University Guangzhou China Comba Telecom Technology (Guangzhou) Limited Department of Electronic Engineering State Key Laboratory of Terahertz and Millimeter Waves City University of Hong Kong China Information and Communication Technology Center CityU Shenzhen Research Institute Shenzhen China Zhejiang Provincial Laboratory of Integrated Circuit Design Hangzhou Dianzi University Hangzhou China

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Impact of Quantization Noise Errors in FPGA Based WLAN Timing Synchronization with the Schmidl and Cox Algorithm

Impact of Quantization Noise Errors in FPGA Based WLAN Timin...

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IEEE International Symposium on circuits and systems

作者： Jorge Torres Gomez Liset Martinez Marrero Matthias Koepp Rajesh Kumar Sharma Tech. Univ. Berlin Berlin Germany Lucerne University of Applied Sciences and Arts Lucerne Switzerland Photonic Networks and Systems Department Fraunhofer Heinrich Hertz Institute Berlin Germany Department of Digital Signal Processing and Circuit Technology Chemnitz University of Technology Chemnitz Germany

ISBN: (纸本)9781728192017;9781728192024

The implementation of accurate solutions to synchronize the transceiver's clocks in real-time operations plays a major role in the current development of communication systems. Considering the orthogonal frequency division multiplexing (OFDM)-based systems, adopted for the deployment of fifth-generation mobile networks (5G), industrial networks, and the wireless local area network (WLAN) standard, several reported solutions focus on field-programmable gate array (FPGA) designs for the clock synchronization in real-time operations. However, reported solutions describe with minor details the impact of the introduced quantization noise error (QNE) based on the implemented bit-width. Their studies provide insights to implement digital solutions of reduced complexity. The current article provides theoretical expressions to characterize accuracy and precision while synchronizing the transmitter's clock. The presented analysis is intended to support designers to evaluate the clock synchronization design considering the bit-width for implementing the given system.

关键词： Wireless LAN Quantization (signal) Real-time systems Synchronization Field programmable gate arrays Standards Clocks

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