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HRI Pioneers Workshop 2013 13

HRI Pioneers Workshop 2013

引用

ACM/IEEE International Conference on Human-Robot Interaction (HRI)

作者： Solace Shen Henny Admoni Caroline Harriott Yunkyung Kim Matt Marge Marynel Vázquez Astrid Rosenthal-von der Pütten Matt Beane Yasuhiko Hato Daniel Lazewatsky Robin Read Steve Vozar Department of Psychology University of Washington Seattle USA Department of Social Psychology University of Duisburg-Essen Duisburg Germany Department of Computer Science Yale University New Haven USA Sloan School of Management Massachusetts Institute of Technology Cambridge USA Department of Electrical Engineering & Computer Science Vanderbilt University Nashville USA Graduate School of Science & Technology Keio University Yokohama Japan Department of Industrial Design Korea Advanced Institute of Science and Technology Daejeon South Korea Industrial & Manufacturing Engineering Oregon State University Corvallis USA Language Technologies Institute Carnegie Mellon University Pittsburgh USA Centre for Robotics & Neural Systems University of Plymouth Plymouth UK Robotics Institute Carnegie Mellon University Pittsburgh USA Department of Mechanical Engineering University of Michigan Ann Arbor USA

ISBN: (纸本)9781467330558

The 2013 Human-Robot Interaction (HRI) Pioneers Workshop, which will be held in conjunction with the 8 th ACM/IEEE International Conference on Human-Robot Interaction, is the premiere venue for student research in the field. This highly selective workshop seeks to foster creativity, communication, and collaboration between the world's top student researchers in the field of human-robot interaction. Pioneers Workshop participants will have the opportunity to learn about the current state of HRI, to present their research, and to network with one another and with select senior researchers in a setting that is less formal and more interactive then the main conference. The theme for this year is Re-envisioning HRI: Dealing With the Elephants in Our Room. The workshop aims to bring forward difficult to discuss issues to help the field achieve more balanced perspectives and a clearer picture of what sort of future we are building.

关键词： Educational institutions Conferences Human-robot interaction Psychology computer science Service robots

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Decentralized iISS robustification of interconnected time-delay systems: A small-gain approach

Decentralized iISS robustification of interconnected time-de...

引用

10th IFAC Workshop on Time Delay systems, TDS-2012

作者： Ito, Hiroshi Pepe, Pierdomenico Jiang, Zhong-Ping Department of Systems Design and Informatics Kyushu Institute of Technology Iizuka Fukuoka 820-8502 Japan Department of Electrical and Information Engineering University of L'Aquila 67040 Poggio di Roio L'Aquila Italy Department of Electrical and Computer Engineering Polytechnic Institute of New York University Brooklyn NY 11201 United States

ISBN: (纸本)9783902823045

In this paper we consider the ISS (input-to-state stability) and iISS (integral input-to-state stability) feedback control redesign for interconnected systems described by retarded nonlinear equations with discontinuous right-hand side. We show that it is possible to design a decentralized controller by which the overall closed-loop system is iISS (ISS) with respect to additive disturbances acting on each subsystem whenever the disturbance-free closed-loop system satisfies a small-gain condition. © 2012 IFAC.

关键词： Time delay

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Power-aware game for cloud computing: A distributed mechanism based on Game Theory for minmizing power consumption in cloud scale datacenter

Power-aware game for cloud computing: A distributed mechanis...

引用

International Symposium on Telecommunications, IST

作者： Hadi Khani Naser Yazdani Siamak Mohammadi Router Laboratory School of Electrical and Computer Engineering University College of Engineering University of Tehran Tehran Iran Dependable Systems Design Laboratory School of Electrical and Computer Engineering University College of Engineering University of Tehran Tehran Iran

The power consumption of datacenters has increased dramatically in recent years. Cloud computing accelerates this increase. The reduction of power consumption has become a challenge for cloud providers in large scale datacenters. They consolidate servers by virtualization technology as an effective remedy for huge power consumption. The management of consolidation often has been performed centrally in datacenters. We devised a distributed self-organized mechanism based on Game Theory for this purpose. In the worst case, our results are only twice as great as the theoretical minimum power consumption. In addition our mechanism could enhance the current centralized ones in two ways. Firstly, it can make decisions with less delay in response to dynamic behavior of usage patterns in cloud computing. Secondly, it can better scale up in pace with the future datacenters.

关键词： Power demand Games Servers Virtual machining Cloud computing Resource management Game theory

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Investigating Dependability of Short-Range Wireless Embedded systems through Hardware Platform Based design

Investigating Dependability of Short-Range Wireless Embedded...

引用

Euromicro Symposium on Digital System design

作者： B. Senouci A.J. Annema M.J. Bentum H.G. Kerkhoff Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty Telecommunication Engineering Group Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation becomes an essential question to answer, and poses several challenges. Obviously, it's particularly difficult to investigate the reliability of such mixed HW/SW IPs based systems. Therefore, dependability has to be investigated at different abstractions levels, and for all components integrated into the system being designed. In this paper, we discuss the investigation of dependability in wireless short range systems. Firstly we show how a HW platform based dependability investigation can be a very interactive approach; secondly, we describe a real experience in building a wireless hardware platform for short range systems dependability analysis, and finally, based on this wireless network platform, we propose a dependability flow that takes care of the heterogeneous parts of the wireless embedded systems.

关键词： Wireless communication Hardware Software computer architecture Communication system security Reliability System-on-a-chip

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Experimentally driven verification of synthetic biological circuits 12

Experimentally driven verification of synthetic biological c...

引用

design, Automation and Test in Europe Conference and Exhibition

作者： Boyan Yordanov Evan Appleton Rishi Ganguly Ebru Aydin Gol Swati Banerjee Carr Swapnil Bhatia Traci Haddock Calin Belta Douglas Densmore Microsoft Research Cambridge UK Departments of Bioinformatics Boston University Boston MA USA Departments of Systems Engineering Boston University Boston MA USA Departments of Molecular and Cell Biology and Biochemistry Boston University Boston MA USA Departments of Electrical and Computer Engineering Boston University Boston MA USA Departments of Bioinformatics and Systems Engineering Boston University Boston MA USA Departments of Bioinformatics Molecular and Cell Biology and Biochemistry Departments of Electrical and Computer Engineering Boston University Boston MA USA

ISBN: (纸本)9783981080186

We present a framework that allows us to construct and formally analyze the behavior of synthetic gene circuits from specifications in a high level language used in describing electronic circuits. Our back-end synthesis tool automatically generates genetic-regulatory network (GRN) topology realizing the specifications with assigned biological “parts” from a database. We describe experimental procedures to acquire characterization data for the assigned parts and construct mathematical models capturing all possible behaviors of the generated GRN. We delineate algorithms to create finite abstractions of these models, and novel analysis techniques inspired from model-checking to verify behavioral specifications using Linear Temporal Logic (LTL) formulae.

关键词： Genetics Proteins Trajectory Regulators Inverters Analytical models Computational modeling

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Automatic detection of pale path and overlaps in chromosome images using adaptive search technique and re-thresholding

Automatic detection of pale path and overlaps in chromosome ...

引用

International Conference on computer Vision Theory and Applications, VISAPP 2012

作者： Ranjan, Rajeev Subasinghe, Akila A. Samarabandu, Jagath Rogan, Peter K. Knoll, Joan H.M. Indian Institute of Technology Electronics and Electrical Communication Engineering Kharagpur India Image Recognition and Intelligent Systems Laboratory Electrical and Computer Engineering University of Western Ontario ON N6A 5B9 Canada Departments of Biochemistry Schulich School of Medicine and Dentistry University of Western Ontario ON N6A 5C1 Canada Departments of Pathology Schulich School of Medicine and Dentistry University of Western Ontario ON N6A 5C1 Canada

ISBN: (纸本)9789898565037

Detection and separation of overlapping and touching chromosomes is a critical issue in image analysis applications for cytogenetics where accurately segmented chromosomes are essential. We present a novel method of automatic pale path detection for all types of stained chromosome images. Optimum number of cut-points for each cluster of touching or overlapping chromosomes is obtained and analysed sequentially for the pale paths. A self-adaptive search window searches for the minimum grayscale intensity beginning from the vicinity of a cut-point and propagates gradually till the end of pale path. Efficient image and area thresholding restricts the faulty detection of touch or overlap in a chromosome cluster.

关键词： Chromosomes

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Slew-aware buffer insertion for through-silicon-via-based 3D ICs

Slew-aware buffer insertion for through-silicon-via-based 3D...

引用

Custom Integrated Circuits Conference (CICC)

作者： Young-Joon Lee Inki Hong Sung Kyu Lim Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Cadence Design Systems San Jose CA USA

Large parasitic capacitances of through-silicon-vias in 3D ICs cause signal slew and delay to increase. We propose a buffer insertion algorithm that further reduces delay by considering slew explicitly. Compared with the well-known van Ginneken algorithm and a commercial 2D tool, our algorithm improves full-chip timing with acceptable runtime overhead.

关键词： Delay Logic gates Through-silicon vias Silicon Capacitance Runtime Mathematical model

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Reproduction and detection of board-level functional failure

Reproduction and detection of board-level functional failure

引用

作者： Fang, Hongxia Chakrabarty, Krishnendu Wang, Zhiyuan Gu, Xinli Encounter Test Department Cadence Design Systems Endicott NY 13760 United States Department of Electrical and Computer Engineering Duke University Durham NC 27708 United States Cisco Systems Inc. San Jose CA 95134 United States Huawei Technologies San Jose CA 95050 United States

No trouble found (NTF) due to functional failures is a common scenario today in board-level testing at system companies. A component on a board fails during the board-level functional test, but it passes the automatic test equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we propose an innovative functional test approach and discrete Fourier transform (DFT) methods for the detection of board-level functional failures. These DFT and test methods allow us to reproduce and detect functional failures in a controlled deterministic environment, and provide ATE tests to the supplier for early screening of defective parts. Experiments on an industry design show that the proposed functional scan test with appropriate functional constraints can adequately mimic the functional state space, as measured by appropriate coverage metrics. Experiments also show that most functional failures due to dominant bridging, crosstalk, and delay faults due to power supply noise can be reproduced and detected by functional scan test. We also describe two approaches to enhance the mimicking of the functional state space. The first approach allows us to select a given number of initial states in linear time and functional scan tests resulting from these selected states are used to mimic the functional state space. The second approach is based on controlled state injection. © 2012 IEEE.

关键词： Discrete Fourier transforms

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IBIS modeling using latency insertion method (LIM)

IBIS modeling using latency insertion method (LIM)

引用

IEEE Workshop on Signal Propagation on Interconnects (SPI)

作者： Jose E. Schutt-Ainé Jilin Tan Ping Liu Feras Al-Hawari Ambrish Varma Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana IL USA Cadence Design Systems Chelmsford MA USA

This paper presents an approach for the transient simulation of I/O buffers described by IBIS models. Using the latency insertion method a formulation can be obtained for the transient behavior of IBIS models and external circuitry. The formulation offers better convergence than traditional Newton-Raphson methods and is therefore more robust. Several computer simulations are performed to validate the method.

关键词： Integrated circuit modeling Abstracts Accuracy

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Performance and characteristics of silicon avalanche photodetectors in the C5 process

Performance and characteristics of silicon avalanche photode...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Dennis Montierth Timothy Strand James Leatham Lloyd Linder R. Jacob Baker Department of Electrical and Computer Engineering Boise State University Boise ID USA FLIR Systems Inc. USA Indepentent IC Circuit Design and Systems Consultant

Avalanche photodetectors (APDs) have been fabricated in ON Semiconductor's C5 process without any special process or fabrication steps. The electrical and optical characteristics of APDs, with varying active area and guard ring configurations, are reported in this paper. Also reported are the details and considerations that went into laying out the APDs. It was found that substrate current was negligible and nearly independent of the geometrical shape of the substrate tie-downs around the perimeter of the APD structures. The measured APD breakdown is approximately 14 V. The devices show optical gains in excess of 1,000 at photocurrents of 10 μA.

关键词： Decision support systems Geometrical optics Integrated optics Optical device fabrication Substrates Optical variables measurement

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