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Conference Record of the IEEE Industry Applications Society Annual Meeting (IAS)

作者： J.M. Guerrero M. Leetmaa F. Briz A. Zamarron R.D. Lorenz Department of Electrical Computer & Systems Engineering University of Oviedo Gijon Spain Department of Mech. Engineering University of Wisconsin Madison Madison WI USA Department of Mech. & Elec. Engineering Technological Institute of León Leon Mexico Departments of ME and ECE University of Wisconsin Madison Madison WI USA

An analysis of PWM inverter nonlinearities influencing high frequency carrier signal voltage injection for saliency-tracking-based rotor/flux position estimation is presented in this paper. Distortion of the injected carrier voltage caused by the nonlinear behavior of the inverter has been reported to cause errors in the estimated rotor/flux position. Though a number of techniques have been developed to compensate for inverter nonlinearities, they have not been proven to be effective when a high frequency, low magnitude voltage needs to be generated. Both the origins of the distortion as well as the requirements for compensation methods to be effective when producing such high frequency voltages is established in this paper.

关键词： Sensorless control Frequency estimation Voltage Pulse width modulation inverters Nonlinear distortion Signal analysis Pulse width modulation Estimation error systems engineering and theory Rotors

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AGENT-BASED SYSTEM ARCHITECTURE FOR DYNAMIC AND OPEN ENVIRONMENTS

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International Journal of Information Technology & Decision Making 2003年第1期2卷 105-133页

作者： ELHADI SHAKSHUKI HAMADA GHENNIWA MAHAMED KAMEL Jodrey School of Computer Science Acadia University Wolfville Canada B4P 2R6 Canada Electrical and Computer Engineering University of Western Ontario London Canada N6G 1H1 Canada Systems Design Engineering University of Waterloo Waterloo Canada N2L 3G1 Canada

The rapid growth of the network-centered (Internet and Intranet) computing environments requires new architectures for information gathering systems. Typically, in these environments, the information resources are dynamic, heterogeneous and distributed. In addition, these computing environments are open, where information resources may be connected or disconnected at any time. This paper presents an architecture for a multi-agent information gathering system. The architecture includes three types of agents: interface, broker and resource agents. The interface agents interact with the users to fulfill their interests and preferences. The resource agents access and capture the content of the information resources. The broker agents facilitate cooperation among the information and the resource agents to achieve their desired goals. This paper provides the agents' architecture, design and implementations that enable them to cooperate, coordinate and communicate with each other to gather information in an open and dynamic environment.

关键词： Software agents cooperation coordination communication

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A Novel, User-Level, Security-On-Demand Paradigm for ATM Networks: Modeling, Simulation, and Performance Analysis

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Journal of Interconnection Networks 2003年第4期4卷 429-461页

作者： H. J. (Jerry) Schumacher Tony Lee Sumit Ghosh Department of EE & CS US Military Academy West Point New York 10996 USA Vitria Technology 945 Stewart Drive Sunnyvvale CA 94086 USA Secure Network Systems Design Lab. Department of Electrical & Computer Engineering Stevens Institute of Technology Hoboken NJ07030 USA

With networks increasingly moving into virtually every aspect of our daily life, security is gaining importance, not only from the traditional perspective of communication but the network's growing role in modern automation and control. The traditional, certification based approach attempts to guarantee the security of a network through certification. Certified networks are generally confined to a limited domain and, as a result, they are isolated, costly, and under-utilized. In contrast, this paper presents a new principle – user-level, security-on-demand system, wherein the network allocates, where possible, the security resources commensurate with the user's request for transporting message(s) through the network securely. This principle is successfully demonstrated for the current Asynchronous Transfer Mode (ATM) networks, and is the result of an integration of the fundamental framework for network security, recently proposed by the authors in the literature, with the unique characteristics of ATM networks. The framework encapsulates the fundamental knowledge and set of relationships in network security and permits scientific and systematic reasoning about network security. It also enables all user groups – military, government, industry, and academia, to define their security requirements in a uniform manner. The security-on-demand approach promises the development of a "mixed use" class of networks in the future that may be simultaneously shared by different groups of users, with the system sustaining the diverse security requirements of each user. A unique characteristic in ATM network design is the dynamic call setup process. Under it, a network first establishes a virtual path or route for a user's call, guided by the user's requirements, and then transports the messages when a route has been successfully determined. This unique ATM characteristic is integrated with the framework to yield a successful demonstration of the proposed, user-level, security-on-d

关键词： network security security metric network security performance security-on-demand distributed resources allocation ATM network total security modeling simulation

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A proposal for routing-based timing-driven scan chain ordering

A proposal for routing-based timing-driven scan chain orderi...

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IEEE International Symposium on Quality Electronic design

作者： P. Gupta A.B. Kahng S. Mantik Department of Electrical and Computer Engineering University of California San Diego La Jolla CA USA University of California San Diego La Jolla CA US Dept. of Electr. & Comput. Eng. California Univ. San Diego La Jolla CA USA Cadence Design Systems Inc. San Jose CA USA

Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wirelength. We take into account timing slacks at all sinks that are affected by scan insertion, to achieve a scan chain ordering that meets timing and has smallest wirelength. For the case where sink timing is not met, we also propose a buffer insertion methodology with minimum wirelength objective. The key contribution of this paper is a method to compute a timing-driven incremental connection suited to scan insertion; this has possible applications in general incremental routing.

关键词： Proposals Costs Timing Routing Flip-flops Registers Pins design for testability Circuit testing Traveling salesman problems

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Internet Congestion Control

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IEEE Control systems 2002年第1期22卷 28-43页

作者： Low, Steven H. Paganini, Fernando Doyle, John C. Departments of Computer Science and Electrical Engineering California Institute of Technology Pasadena CA 91125 United States Department of Electrical Engineering University of California Los Angeles CA 90095 United States Departments of Electrical Engineering and Control and Dynamical Systems California Institute of Technology Pasadena CA 91125 United States

This article reviews the current transmission control protocol (TCP) congestion control protocols and overviews recent advances that have brought analytical tools to this problem. We describe an optimization-based framework that provides an interpretation of various flow control mechanisms, in particular, the utility being optimized by the protocol's equilibrium structure. We also look at the dynamics of TCP and employ linear models to exhibit stability limitations in the predominant TCP versions, despite certain built-in compensations for delay. Finally, we present a new protocol that overcomes these limitations and provides stability in a way that is scalable to arbitrary networks, link capacities, and delays.

关键词： Internet Stability Control systems Delay Access protocols Size control IP networks Feedback Analytical models Aggregates

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Topology of the conceptual network of language

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Physical Review E 2002年第6期65卷 065102(R)-065102(R)页

作者： Adilson E. Motter Alessandro P. S. de Moura Ying-Cheng Lai Partha Dasgupta Department of Mathematics Center for Systems Science and Engineering Research Arizona State University Tempe Arizona 85287 Instituto de Física Universidade de São Paulo Caixa Postal 66318 05315-970 São Paulo Brazil Departments of Electrical Engineering and Physics Arizona State University Tempe Arizona 85287 Department of Computer Science and Engineering Arizona State University Tempe Arizona 85287

We define two words in a language to be connected if they express similar concepts. The network of connections among the many thousands of words that make up a language is important not only for the study of the structure and evolution of languages, but also for cognitive science. We study this issue quantitatively, by mapping out the conceptual network of the English language, with the connections being defined by the entries in a Thesaurus dictionary. We find that this network presents a small-world structure, with an amazingly small average shortest path, and appears to exhibit an asymptotic scale-free feature with algebraic connectivity distribution.

关键词： .appears sense topology Conceptual connected words connections connectivity small-world network of language similar concepts cognitive science Thesaurus dictionary average shortest

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Consistency analysis of reconfigurable dataflow specifications

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Workshop on systems, Architectures, Modeling, and Simulation, SAMOS 2001

作者： Bhattacharya, Bishnupriya Bhattacharyya, Shuvra S. Cadence Design Systems San JoseCA95134 United States Department of Electrical and Computer Engineering Institute for Advanced Computer Studies University of Maryland College ParkMD20742 United States

ISBN: (纸本)3540433228

Parameterized dataflow is a meta-modeling approach for incorporating dynamic reconfiguration capabilities into broad classes of dataflow-based design frameworks for digital signal processing (DSP). Through a novel formalization of dataflow parameterization, and a disciplined approach to specifying parameter reconfiguration, the parameterized dataflow framework provides for automated synthesis of robust and efficient embedded software. Central to these synthesis objectives is the formulation and analysis of consistency in parameterized dataflow specifications. Consistency analysis of reconfigurable specifications is particularly challenging due to their inherently dynamic behavior. This paper presents a novel framework, based on a concept of local synchrony, for managing consistency when synthesizing implementations from dynamicallyreconfigurable, parameterized dataflow graphs. © Springer-Verlag Berlin Heidelberg 2002.

关键词： Parameterization

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Analysing trade-offs in scan power and test data compression for systems-on-a-chip

Analysing trade-offs in scan power and test data compression...

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作者： Rosinger, P.M. Gonciari, P.T. Ai-Hashimi, B.M. Nicolici, N. Electronic Systems Design Group Department of Electronics and Computer Science University of Southampton Southampton SO17 1BJ United Kingdom Computer-Aided Design and Test Research Group Department of Electrical and Computer Engineering McMaster University 1280 Main St. W. Hamilton Ont. L8S 4K1 Canada

The relationship is investigated between test data compression and power dissipation during scan testing. It is shown how combining a proposed symmetric coding scheme and a weighted scan latch reordering (W-SLR) algorithm allows efficient exploration of the scan power and test data compression solution space. This is achieved by reducing and balancing the transition activity in the scan-in and scan-out sequences. This will impact the test data compression, which depends only on the scan-in sequence, and the overall scan power dissipation, which depends on the scan-in and scan-out sequences. Trade-off analysis using ISCAS89 benchmark circuits shows that, by employing the proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can easily and explicitly control the scan power and volume of test data. The proposed asymmetric/symmetric code transformation is equally applicable to (and thus it maintains its benefits) any asymmetric 'run length' coding scheme.

关键词： Data compression

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Exploring design through wearable computing art(ifacts)

Exploring design through wearable computing art(ifacts)

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Conference on Human Factors in Computing systems, CHI EA 2002

作者： Garabet, Angela Mann, Steve Fung, James Systems Design Engineering University of Waterloo 200 University Ave.W. Waterloo ON N2L 3G1 Canada Dept. of Electrical and Computer Engineering University of Toronto 10 King's College Road Toronto ON M5S 3G4 Canada

ISBN: (纸本)1581134541

Usability is taken into account in design, however analysis of underlying technological values (such as trust, privacy, security) might become overlooked. In this paper, we illustrate how performance art can be used to elicit information about device design and usage. Wearable computing devices or art(ifacts) were used to spark behavior and debate. It was found that the degree of acceptability of the design was related to the perceived control the wearer had over the device. We suggest that what is learned from performance art can be incorporated into future design.

关键词： Arts computing

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Synchronous interlocked pipelines

Synchronous interlocked pipelines

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作者： Jacobson, Hans M. Kudva, Prabhakar N. Bose, Pradip Cook, Peter W. Schuster, Stanley E. Mercer, Eric G. Myers, Chris J. Design Automation Department IBM T.J. Watson Research Center United States High Performance Systems Department IBM T.J. Watson Research Center United States Department of Electrical and Computer Engineering University of Utah United States

In a circuit environment that is becoming increasingly sensitive to dynamic power dissipation and noise, and where cycle time available for control decisions continues to decrease, locality principles are becoming paramount in controlling advancement of data through pipelined systems. Achieving fine grained power down and progressive pipeline stalls at the local stage level is therefore becoming increasingly important to enable lower dynamic power consumption while keeping introduced switching noise under control as well as avoiding global distribution of timing critical stall signals. It has long been known that the interlocking properties of asynchronous pipelined systems have a potential to provide such benefits. However, it has not been understood how such interlocking can be achieved in synchronous pipelines. This paper presents a novel technique based on local clock gating and synchronous handshake protocols that achieves stage level interlocking characteristics in synchronous pipelines similar to that of asynchronous pipelines. The presented technique is directly applicable to traditional synchronous pipelines and works equally well for two-phase clocked pipelines based on transparent latches, as well as one-phase clocked pipelines based on master-slave latches. © 2002 IEEE.

关键词： Pipelines

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