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IEEE Topical Meeting on electrical Performance of Electronic Packaging (EPEPS)

作者： S. Pannala J. Bandyopadhyay M. Swaminathan M. Torres L. Smith X. Yuan G. Fitzgerald Packaging Research Center Georgia Institute of Technology Atlanta GA USA School of Electrical & Computer Engineering Packaging Research Center Georgia Institute of Technology Atlanta GA USA SUN Microsystems Inc. Palo Alto CA USA Cadence Design Systems Chelmsford MA USA

This paper discusses the pulse propagation effects on lossy thin film package planes. The ground bounce phenomena produced by the resonance on planes has been captured using a combination of modeling techniques and measurements. A macromodeling method has been used to explain the transient phenomena by using the dominant poles and residues of the system.

关键词： Resonance Transistors Dielectric thin films Packaging Power system transients Time domain analysis Frequency domain analysis Sampling methods Frequency measurement Switching circuits

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Synthesis of testable RTL designs

Synthesis of testable RTL designs

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International Conference on VLSI design

作者： C.P. Ravikumar S. Gupta A. Jajoo Dept. of Electr. Eng. Indian Inst. of Technol. New Delhi India Information and Computer Sciences University of California Irvine USA Department of Electrical Engineering Indian Institute of Technology New Delhi India Cadence Design Systems Private Limited Noida Uttar Pradesh India

With several commercial tools becoming available, the high-level synthesis of application-specific integrated circuits is finding wide spread acceptance in VLSI industry today. Existing tools for synthesis focus on optimizing cost while meeting performance constraints or vice versa. Yet, verification and testing have emerged as major concerns of IC vendors since the repercussions of chips being recalled are far-reaching. In this paper, we concentrate on the synthesis of testable RTL designs using techniques from Artificial Intelligence. We present an adaptive version of the well known Simulated Annealing algorithm and describe its application to a combinatorial optimization problem arising in the high-level synthesis of digital systems. The conventional annealing algorithm was conceived with a single perturb operator which applies a small modification to the existing solution to derive a new solution. The Metropolis criterion is then used to accept or reject the new solution. In some of the complex optimization problems arising in VLSI design, a set of perturb functions become necessary, leading to the question of how to select a particular function for modifying the current system configuration. The adaptive algorithm described here uses the concept of reward and penalty from the theory of learning automata to "learn" to apply the appropriate perturb function. We have applied both the conventional simulated annealing algorithm and the adaptive simulated annealing algorithm to the problem of testability-oriented datapath synthesis for signal processing applications. Our experimental results indicate that the adaptive algorithm can yield better solutions in shorter time.

关键词： Signal processing algorithms Simulated annealing Integrated circuit synthesis Circuit testing High level synthesis Very large scale integration Adaptive algorithm Application specific integrated circuits Constraint optimization Cost function

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Hardware-software co-design of embedded systems: the POLIS approach

Hardware-software co-design of embedded systems: the POLIS a...

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1997年

作者： Felice Balarin Massimiliano L Chiodo Paolo Di Giusto Harry Chia Chang Hsieh Attila Jurecska Luciano Lavagno Claudio Passerone Alberto Luigi Sangiovanni-Vincentelli Ellen Marie Sentovich Kei Suzuki Bassam Tabbara

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POCS based error concealment for packet video

POCS based error concealment for packet video

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Data Compression Conference (DCC)

作者： G.-S. Yu M.W. Marcellin M.M.-K. Liu Sony Semiconductor Company of America USA Department of Electrical & Computer Engineering University of Arizona Tucson USA Quickturn Design Systems Inc. USA

Summary form only given. This paper proposes a new error concealment algorithm for packet video, effectively eliminating error propagation effects. Most standard video codecs use motion compensation to remove temporal redundancy. With such motion compensated interframe processing, any packet loss may generate serious error propagation over more than 10 consecutive frames. This kind of error propagation leads to perceptually annoying artifacts. Thus, proper error concealment algorithms need to be used to reduce this effect. The proposed algorithm adopts a one pixel block overlap coding structure to solve the error propagation problem. If no packet loss occurs, the decoded pixel intensities on the overlap areas should be consistent (with small differences caused by quantization error). When a packet loss occurs, the corresponding reconstructed frame and any frames referring to it are all damaged. Such damage causes inconsistent pixel intensities on the overlap areas of damaged frames. The proposed error concealment method poses the packet loss recovery problem as one of parameter estimation. Lost transform coefficients are estimated by the method of projection onto convex sets (POCS). The estimation is performed in a manner that maximizes the consistency of pixel intensities in the overlap areas of the reconstructed frames. Experimental results (using a modified version of CCITT H.261) show that it can have good error concealment results even when the damaged frame loses all the DCT coefficients.

关键词： computer errors Code standards Video codecs Redundancy Propagation losses Decoding Quantization Parameter estimation Convergence Discrete cosine transforms

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Multifractal processing of speech signals

Multifractal processing of speech signals

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International Conference on Information, Communications and Signal Processing

作者： A.Z.R. Langi K. Soemintapura W. Kinsner Laboratory of Microelectronics Design Institute of Technology Bandung InterUniversity Microelectronics Centre Bandung West Java Indonesia Laboratory for Signals and Systems Department of Electrical Engineering Institute of Technology Bandung West Java Indonesia Department of Electrical and Computer Engineering University of Manitoba Winnipeg MAN Canada

This paper describes a novel framework in processing speech signals using multifractality concepts, and shows that multifractality could be a new fundamental tool for speech processing. New approaches using the self-similarity model of complexity have been developed to simplify processing of complicated speech signals. The approaches associate signals with fractal sets and then characterize the sets using real numbers called fractal dimensions. This paper extends the approaches by associating speech signals with measures and then characterizing the measures with multifractal curves such as Mandelbrot dimensions (denoted as f(/spl alpha/)) or Renyi dimensions D/sub q/. Such curves (also known as singularity curves) are the characterization of speech signals. This paper shows that multifractal (or singularity) processing of speech is capable of providing important processing aspects: decomposition, representation, and spectrum characterization-a capability that makes Fourier processing of signals is fundamental. The multifractal approach can decompose speech into various segments based on variations of the segment's Holder exponents. The results can be used for new speech segmentation schemes. The multifractal approach is also used in characterizing speech through singularity spectrum. This can be used to develop better accuracy speech recognition schemes. Finally, the paper describes a process to reconstruct speech signals from their singularity representation, by the means of the so-called wavelet maxima.

关键词： Fractals Speech processing Signal processing Speech recognition Laboratories Microelectronics Fourier transforms Time measurement Signal design Java

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Modeling reverse short channel and narrow width effects in small size MOSFET's for circuit simulation

Modeling reverse short channel and narrow width effects in s...

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International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yuhua Cheng T. Sugii Kai Chen Zhihong Liu Min-Chie Jeng Chenming Hu Department of Electrical Engineering and Computer Sciences University of California Berkeley CA USA ULSI Technology Laboratory Fujitsu Laboratories Limited Atsugi Japan BTA Technologies Inc. Santa Clara CA USA Cadence Design Systems Santa Clara CA USA

Modeling of small size MOSFETs and experimental verification of the model using devices with varying pocket implant processes are presented. The results show that the model can describe reverse short channel and narrow width effects and match the measured characteristics of threshold voltage and saturation current over a wide range of channel lengths and widths down to 0.12 /spl mu/m regime.

关键词： MOSFET circuits Circuit simulation Threshold voltage Implants Semiconductor process modeling Doping Length measurement Data mining Solid modeling Immune system

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ISO certification and the Department of Defense

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NAVAL ENGINEERS JOURNAL 1997年第5期109卷 77-81页

作者： Scott, H Kuehn, RG P.E. Howard Scott RE. (B.S.I.E. M.B.A. M.S.E.):has worked in the steel industry proprietary confectionery businesses and the food industry. He has worked as an industrial engineer supervisor of industrial engineering corporate staff engineer and a production manager. Since his return to the Naval Surface Warfare Center Crane Division he has worked as a computer systems analyst project engineer project manager and branch manager. He also teaches evening college classes. Randy G. Kuehn:has a B.S. degree in electrical engineering. Since 1970 he has held numerous positions at the Naval Surface Warfare Center involving engineering management and supervision. He has been project engineer and in service engineering agent on complex electronic systems and directed the development of design changes and maintenance programs on these systems. He has also served on Navy review teams overseeing and directing contractor production and development projects.

The leaders of the United States Government are advocating a new way of doing business, because the Department of Defense (DoD) budget has been declining since the Reagan administration. With this decline comes the realization that private industry and the government can no longer afford the detailed government funded standards and related management bureaucracy. The value added by these standards is not visible to the higher-levels of the DoD. In an economy that is turning global, an international (non-governmental sponsored) standard such as ISO 9000 (ISO) has high appeal. ISO does not do away with standards, it is one. ISO provides uniformity and standardization via training of registrars, certification of processes, and periodic audits. A more consistent set of audit findings allows managers to focus on product and functional issues. The Coast Guard Yard at Baltimore, Maryland and the Naval Surface Warfare Center Carderock Division are already certified and the Naval Surface Warfare Center Crane Division is now joining them. The lessons learned are: know the registrar, plan, work the plan, and learn from others. Most of all, get management support at all levels.

关键词： Military engineering

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Operational systems, logistics engineering and technology insertion

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NAVAL ENGINEERS JOURNAL 1997年第3期109卷 205-220页

作者： Grubb, MJ Skolnick, A Michael J. Grubb:has perfomzed naval engineering at the Crane Division Naval Surface Warfare Center (NSWC) for more than twenty-five years. He currently the program manager for the Sustainable Hardware and Affordable Readiness Practice Program (SHARP). is a Navy-wide logistics research and development prgram aimed at the successful transiton of proved technologies inot the fleet. SHARP focuses on reducing acquisition performance capability reliability maintainability and readiness of these systems. Mr. Grubb has served as a department director for the past eleven years. His most recent assignment was as director of the Tactical Computer Resources and Test Equipment Department. This organization provided acquisition and in-service engineering support of the Navy's tectical embedded computers priphirals displays and mass memory storage devices. The organization also provided a complete range of product engineering and metrology engineerig services for SSP NevSeaSysCom and the Trident Program. Prior to this appointment Mr. Grubb was deptuy director psysical security programs department and site responsible for program management and system integration of ashore integrated security systems. Mr. Grubb holds a B.S. degree in industrial engineering from Iowa State Universtiy an M.S. degree in industrial engineering from Purdue University and has copleted the course work (Dec.'96 for a master's degree in public and environment affairs at Indiana University-Purdue Univeristy Indianapolis. Dr. Alfred Skolnick operates System Science Consultants (SSC) specilizing in strategic planning technical program definiton technology assessment and engineering analyses on selected matters of national interest. He has taught physics mathematics and management sciences at University of Virginia and Marymount University and is currently adjunct professor of mathematics at Northern Virginia Community College. Form 1985 to 1989 he was president of the American Society of Noval Engineers. Dr. Skolnick served at Applied Physic

In an era of fiscal austerity, downsizing and unforgiving pressure upon human and economic capital, it is an Augean task to identify resources for fresh and creative work. The realities of the day and the practical demands of more immediate fleet needs can often dictate higher priorities. Yet, the Navy must avoid eating its seed corn. Exercising both technical insight and management foresight, the fleet, the R&D community, the Office of the Chief of Naval Operations (OpNav) and the product engineering expertise of the Naval Surface Warfare Center (NSWC) are joined and underway with integrated efforts to marry new, fully demonstrated technologies and operational urgencies. Defense funding today cannot sponsor all work that can be mission-justified over the long term because budgets are insufficient to support product maturation within the classical development cycle. However, by rigorous technical filtering and astute engineering of both marketplace capabilities and currently available components, it is possible in a few select cases to compress and, in effect, integrate advanced development (6.3), engineering development (6.4), weapon procurement (WPN), ship construction (SCN), operation and maintenance (O&M,N) budgetary categories when fleet criticalities and technology opportunities can happily meet. In short, 6.3 funds can be applied directly to ''ripe gateways'' so modern technology is inserted into existing troubled or aging systems, sidestepping the lengthy, traditional development cycle and accelerating practical payoffs to recurrent fleet problems. To produce such constructive results has required a remarkable convergence of sponsor prescience and engineering workforce excellence. The paper describes, extensively, the philosophy of approach, transition strategy, polling of fleet needs, technology assessment, and management team requirements. The process for culling and selecting specific candidate tasks for SHARP sponsorship (matching operational need with t

关键词： Naval vessels

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Transparent random access memory testing for pattern sensitive faults

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JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 1996年第3期9卷 251-266页

作者： Karpovsky, MG Yarmolik, VN Research Laboratory of Design and Testing of Computer Hardware Department of Electrical Computer and Systems Engineering Boston University Boston USA

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k-1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the rest and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.

关键词： random access memory memory testing exhaustive memory testing transparent memory testing built-in self-test pseudo-exhaustive memory testing pattern sensitive faults signature analysis

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The Flexible Hypercube: A New Topology Suitable for Use in Metropolitan Area Networks

The Flexible Hypercube: A New Topology Suitable for Use in M...

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IEEE Workshop on Local and Metropolitan Area Networks (LANMAN)

作者： T. Hameenanttila Xin-Li Guan J.D. Carothers Jian-Xin Chen The University of Arizona Computer Systems Design Laboratory Department of Electrical and Computer Engineering University of Arizona Tucson Tucson AZ USA

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