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International Symposium on Fault-Tolerant Computing (FTCS)

作者： R.K. Iyer D.J. Rossetti CENTER FOR RELIABLE COMPUTING Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

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Yield enhancement vs. performance improvement in VLSI circuits

Yield enhancement vs. performance improvement in VLSI circui...

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IEEE International Symposium on Semiconductor Manufacturing

作者： V.K.R. Chiluvuri I. Koren Semiconductor Systems Design Technology Motorola Austin TX USA Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

For advanced submicron VLSI technologies maintaining higher performance and better yield is a challenging task. Layout optimization for improving yield may affect the circuit performance and vice versa. We analyse the effect of layout modifications for parasitic capacitance reduction on yield in this paper. Our results show that the solutions to the yield enhancement and parasitic capacitance reduction problems are very close to each other.

关键词： Very large scale integration Integrated circuit interconnections Wire Delay Minimization Parasitic capacitance Routing Manufacturing Compaction Integrated circuit yield

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Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing 95

Orthogonal greedy coupling: a new optimization approach to 2...

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Proceedings of the 32nd annual ACM/IEEE design Automation Conference

作者： Yu-Liang Wu Malgorzata Marek-Sadowska Cadence Design Systems Inc. San Jose CA Department of Electrical and Computer Engineering University of California Santa Barbara CA

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Layout optimization using arbitrarily high degree posynomial models

Layout optimization using arbitrarily high degree posynomial...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： P.K. Sancheti S.S. Sapatnekar Cadence Design Systems Inc. Chelmsford MA USA Department of Electrical and Computer Engineering Iowa State University Ames IA USA

The problem of designing individual macrocells for a library with power and speed considerations is addressed here. A new technique for optimization using posynomial approximating functions is devised. In the design of each macrocell, optimality in design is critical and highly accurate techniques for measuring the performance are required during optimization. This paper presents methods for accurately estimating the worst-case contribution of the power and delay of a cell to a circuit. The program uses circuit-level simulation to calculate the power dissipation and delay of the cell with the highest accuracy. A rationale for using arbitrary degree posynomial modeling functions for area, delay and power modeling is presented. The problem is then formulated as a convex programming problem, and a rigorous optimization technique is used to arrive at the optimal macrocell.

关键词： Macrocell networks Power dissipation design optimization Delay estimation Power system modeling Circuit simulation Semiconductor device modeling CMOS digital integrated circuits Digital circuits Libraries

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Sequential synthesis using S1S 95

Sequential synthesis using S1S

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Proceedings of the 1995 IEEE/ACM international conference on computer-aided design

作者： Adnan Aziz Felice Balarin Robert Brayton Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of California at Berkeley Berkeley CA Cadence Design Systems Cadence Berkeley Laboratories Berkeley CA

ISBN: (纸本)9780818672132

We present a mathematical framework for analyzing the synthesis of interacting finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems.

关键词： S1S

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Fault emulation: a new approach to fault grading

Fault emulation: a new approach to fault grading

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IEEE International Conference on computer-Aided design

作者： Kwang-Ting Cheng Shi-Yu Huang Wei-Jin Dai Department of Electrical & Computer Engineering University of California Santa Barbara CA USA Quickturn Design Systems Inc. Mountain View CA USA

ISBN: (纸本)0818672137

In this paper, we propose a method of using an FPGA-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the run-time of fault grading, which is one of the most resource-intensive tasks in the design process. A serial fault emulation algorithm is employed and enhanced by two speed-up techniques. First, a set of independent faults can be emulated in parallel. Second, simultaneous injection of multiple dependent faults is also possible by adding extra supporting circuitry. Because the reconfiguration time spent on mapping the numerous faulty circuits into the FPGA boards could be the bottleneck of the whole process, using extra logic for injecting a large number of faults per configuration can reduce the number of reconfigurations, and thus, significantly improve the efficiency. Some modeling issues that are unique in the fault emulation environment are also addressed. The performance estimation indicates that this approach could be several orders of magnitude faster than the existing software approaches for large designs.

关键词： Emulation Circuit faults Hardware Field programmable gate arrays Circuit simulation Logic design Process design design for testability Programmable logic arrays Logic programming

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Routing on regular segmented 2-D FPGAs

Routing on regular segmented 2-D FPGAs

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Asia and South Pacific design Automation Conference

作者： Yu-Liang Wu M. Marek-Sadowska Cadence Design Systems Inc. San Jose CA USA Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

In this paper we analyze the properties of the Xilinx-like regular segmentation schemes for 2-D Field Programmable Gate Arrays (FPGAs). We introduce a new notion of architectural level routing decaying effect caused by wiring segmentation. We discuss its routing properties and propose a relative prime number based segmentation scheme for 2-D FPGA architectures. A new FPGA design concept of applying architectural coupling to achieve better routability is also introduced and experimentally justified.

关键词： Routing Field programmable gate arrays Wire Switches Logic Topology Wiring computer architecture Switching circuits Active circuits

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Sequential synthesis using S1S

Sequential synthesis using S1S

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IEEE International Conference on computer-Aided design

作者： A. Aziz F. Balarin R. Brayton A. Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences University of California Berkeley Berkeley CA USA Cadence Design Systems Cadence Berkeley Laboratories Berkeley CA USA

We present a mathematical framework for analyzing the synthesis of interacting, finite state systems. The logic S1S is used to derive simple, rigorous, and constructive solutions to problems in sequential synthesis. We obtain exact and approximate sets of permissible FSM network behavior, and address the issue of FSM realizability. This approach is also applied to synthesizing systems with fairness and timed systems.

关键词： Automata Network synthesis Logic design automation Very large scale integration design optimization Laboratories Modems Process design Digital systems

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PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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A DISTRIBUTED MEDIA ACCESS PROTOCOL FOR PACKET RADIO NETWORKS AND PERFORMANCE ANALYSIS .2. NETWORK SET-UP TIME AND DATA RATE

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INTERNATIONAL JOURNAL OF COMMUNICATION systems 1995年第1期8卷 49-63页

作者： POND, LC LI, VOK Communication Sciences Electrical Engineering Systems University of Southern California Los Angeles CA 90089-2565 U.S.A. Lawrence C. Pond received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Southern California in 1983 and 1990 respectively. Dr. Pond is currently a scientist at Hughes Space and Communications Company having joined in 1980. He has worked in the fields of communication system design mobile communication network and spacecraft payload design. He is currently working on the development of satellite-based ATM transport and switching architectures for BISDN and Defense Information System Network amlications. Dr. Pond is a member of IEEE. Victor O. K. Li was born in Hong Kong in 1954. He received his SB SM and Sc.D. degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology Cambridge Massachusetts in 1977 1979 and 1981 respectively. Since February 1981 he has been with the University of Southern California (USC) LOS Angeles California where he is Professor of Electrical Engineering and Director of the USC Communication Sciences Institute. He has published 150 technical papers and has lectured and consulted extensively around the world. His research interests include high-speed communication networks personal communication networks intelligent networks distributed databases queueing theory graph theory and applied probability. Dr. Li is very active in the Institute of Electrical and Electronic Engineers (IEEE) having been a member of the Computer Communications Technical Committee since 1983 and having served as Chairman from 1987–1989. He served as Chairman of the Los Angeles Chapter of the IEEE Information Theory Group from 1983–1985. He is the Steering Committee Chair of the International Conference on Computer Communications and Networks (IC3 N) General Chair of the 1st Annual IC3N held in San Diego California in June 1992 General Chair and Technical Program Chair of the 4th IEEE Workshop on Comp

In this, the second part of a two-part paper, the required time for establishing a mobile packet radio network using the virtual circuit and time division multiple access protocol developed in Part 1 is analysed. Tools are developed to determine the virtual circuit and network set-up times in terms of the channel bandwidth allocated to establish and maintain the network. The tools are then extended to include the effects of user mobility. Then these results are combined with the network capacity results of Part 1 to analyse the trade-off between the data rate and set-up time of the network. Next a hierarchical architecture is proposed and the network data rate versus set-up time trade-off of this architecture is analysed using these tools. This architecture is shown to both provide a higher data rate and establish faster than flat networks of the same number of nodes.

关键词： PACKET RADIO NETWORK EPLRS DISTRIBUTED NETWORK TDMA VIRTUAL CIRCUITS MULTIHOP NETWORK BOUNDED DELAY MOBILITY NETWORK SET-UP TIME HIERARCHICAL NETWORK NETWORK DATA RATE

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