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Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Robust multiscale triangle-area representation for 2D shapes

Robust multiscale triangle-area representation for 2D shapes

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IEEE International Conference on Image Processing

作者： I. El Rube N. Alajlan M. Kamel M. Ahmed G. Freeman Systems Design Engineering University of Waterloo Waterloo ONT Canada Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada Physics and Computer Science Department Wilfrid Laurier University Waterloo ONT Canada

In this paper, a new 2D shape multiscale triangle-area representation (MTAR) is proposed. This representation utilizes a simple geometric principle, the area of a triangle, in obtaining a robust and efficient shape representation. The use of the wavelet transform for decomposing the boundary of the shapes improves the efficiency and robustness of the representation. The MTAR is more robust to the affine transformation, less affected by noise, and more selective than similar methods, e.g., the curvature scale-space CSS. Two tests, using MPEG-7 CE-shape-1 database, show that MTAR achieves better performance than the CSS under affine transformation and in the general shape retrieval.

关键词： Shape Cascading style sheets Noise robustness design engineering Noise shaping MPEG 7 Standard Robust stability Image segmentation Smoothing methods systems engineering and theory

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Comment on “Inability of Lyapunov Exponents to Predict Epileptic Seizures”

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Physical Review Letters 2005年第1期94卷 019801-019801页

作者： Leonidas D. Iasemidis Konstantinos Tsakalis J. Chris Sackellares Panos M. Pardalos The Harrington Department of Bioengineering Arizona State University Tempe Arizona 85287 USA Department of Electrical Engineering Arizona State University Tempe Arizona 85287 USA Departments of Neurology Neuroscience Pediatrics Psychiatry and Biomedical Engineering University of Florida Gainesville Florida 32611 USA Departments of Industrial and Systems Engineering Computer Science and Biomedical Engineering University of Florida Gainesville Florida 32611 USA

A Comment on the Letter by Ying-Cheng Lai et al., Phys. Rev. Lett. 91, 068102 (2003). The authors of the Letter offer a Reply.

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An Alternative Approach on Three-Dimensional Space-Vector Modulation of Three-Phase Inverters

An Alternative Approach on Three-Dimensional Space-Vector Mo...

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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： P. Rodriguez J. Pou R. Pindado J. Montanya R. Burgos D. Boroyevich Universitat Politecnica de Catalunya Institut de Tecniques Energetiques Barcelona Catalunya ES Departments of Electrical and Electronic Engineering Power Quality and Renewable Energy (QuPER) EUETIT Technical University of Catalonia Terrassa Spain Departments of Electrical and Electronic Engineering Power Quality and Renewable Energy (QuPER) Terrassa SPAIN Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Virginia Polytechnic Institute and State University Blacksburg VA USA Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Blacksburg VA USA

This paper presents a new standpoint on the analysis of the space-vector modulation (SVM) in three-phase inverters. By means of a three-dimensional (3D) approach, a mathematically and physically sound explanation of the modulation process is obtained. As it is well known, a three-phase two-level voltage source inverter has eight switching states, which give rise to eight generating vectors (two of them are the zero-vectors). Taking into account that the reference voltage vector is synthesized by these generating vectors, it seems interesting to translate the reference vector from the natural a-b-c reference base to a new one, which is directly based on the generating vectors (generating base). In this new base, one of the three unitary vectors always follows the direction of the zero-vectors (zero-sequence axis). Moreover, in a three-leg full-bridge (TLFB) inverter, the voltage synthesized over the zero-sequence axis does not appear in the load side. Therefore, it is logical to cancel the contribution of the zero-vectors on the inverter output in order to obtain the maximum use of the dc-link voltage. This cancellation is really easy when the reference vector is expressed on the new generating base, since it is only necessary to eliminate the zero-vectors direction component. As a result of this analysis, a very efficient three-dimensional space-vector modulation (3D-SVM) algorithm is introduced. In this algorithm, the modulator input variables are given in the natural a-b-c reference frame. The proposed modulation method rests on the well-known carried-based modulation technique, and avoids trigonometric calculations, definition of optimal sequences, and control of the switching intervals. The proposed 3D-SVM technique is verified by simulation and experiment

关键词： Support vector machines Pulse width modulation inverters Optimal control Pulse width modulation Zero voltage switching Algorithm design and analysis Input variables Voltage control Switches Motor drives

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Three-dimensional SVM for modular power electronics systems

Three-dimensional SVM for modular power electronics systems

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Annual Conference of Industrial Electronics Society

作者： P. Rodriguez J. Pou A. Luna D. Ghizoni J. Guo G. Francis R. Burgos D. Boroyevich Power Quality and Renewable Energy (QuPER) Departments of Electrical and Electronic Engineering Technical University of Catalonia Barcelona Spain Center for Power Electronics Systems (CPES) Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg VA USA

Space vector modulation (SVM)-based on the explicit control of converter switching states-is not the most suitable approach for the modulation of modular power electronics systems due to its apparent lack of modeling flexibility. This paper addresses this issue by presenting a new analytical standpoint for the analysis of SVM in modular power conversion systems, namely power electronics building blocks (PEBB)-based systems. Specifically, the paper presents a mathematically and physically sound modulation technique for PEBB-based converters developed by means of a three-dimensional (3D) space-vector representation. As a result, a processing efficient three-dimensional space-vector modulation algorithm is proposed (3D-SVM). The algorithm itself rests on the well-known carrier-based pulse width modulation technique, therefore it does not require any trigonometric calculations, definitions of optimal sequences, and direct control over the switching states of the three-phase converter. The proposed 3D-SVM technique is verified by simulation and experimental results obtained with a three-phase power converter using 33 kW IGBT-based PEBB modules.

关键词： Support vector machines Pulse width modulation inverters Power electronics Pulse width modulation converters Switching converters Voltage control Signal synthesis Power quality Renewable energy resources Power engineering and energy

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Fast-processing modulation strategy for the neutral-point-clamped converter with total elimination of the low-frequency voltage oscillations in the neutral point

Fast-processing modulation strategy for the neutral-point-cl...

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Annual Conference of Industrial Electronics Society

作者： J. Pou P. Rodriguez V. Sala J. Zaragoza R. Burgos D. Boroyevich Power Quality and Renewable Energy (QuPER) Research Group Departments of Electronic and Electrical Engineering Technical University of Catalonia Catalonia Spain Center for Power Electronics Systems (CPES) Department of Electrical and Computer Engineering Virginia Polytechnic Institute Virginia Tech State University VA USA

This paper presents a novel modulation strategy for the neutral-point-clamped converter. This strategy overcomes one of the main problems of this converter, which is the low-frequency voltage oscillation that appears in the neutral point under some operating conditions. The proposed modulation strategy can completely remove this oscillation for all the operating points and for any kind of loads, even unbalanced and nonlinear loads. The algorithm is based on a carrier-based PWM. Nevertheless, it can generate the maximum output voltage amplitudes attainable under linear modulation, such as space-vector modulation. Furthermore, this technique can be implemented with a very simple algorithm, and hence can be processed very quickly. A control loop for balancing the voltages on the DC-link capacitors is also proposed. This balancing strategy is designed so that it does not increase the switching frequencies of the devices when it is applied to the converter. The proposed modulation technique is verified by simulation and experiment

关键词： Pulse width modulation Capacitors Voltage control Amplitude modulation Switching frequency Topology Power quality Renewable energy resources Power electronics Switching converters

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Double Synchronous Reference Frame PLL for Power Converters Control

Double Synchronous Reference Frame PLL for Power Converters ...

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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： P. Rodriguez J. Pou J. Bergas I. Candela R. Burgos D. Boroyevich Departments of Electrical and Electronic Engineering Power Quality and Renewable Energy (QuPER) Technical University of Catalonia (UPC) Terrassa Spain Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Virginia Polytechnic Institute and State University (Virginia Tech) Blacksburg VA USA

This paper deals with one of the most important issues in the control of grid-connected converters, which is the detection of the positive sequence fundamental component of the utility voltage. The study carried out in this paper conducts to a fast, precise, and robust positive sequence voltage detector offering a good behavior, even if unbalanced and distorted conditions are present in the grid. The proposed detector utilizes a new "double synchronous reference frame PLL" (DSRF-PLL), which completely eliminates the existing errors in conventional synchronous reference frame PLL systems (SRF-PLL) when operating under unbalanced utility voltages. In the study performed in this paper, the positive and negative sequence components of the unbalanced voltage vector are properly characterized. When this unbalanced vector is expressed on the DSRF, the analysis of the signals on the DSRF axes permits to design a decoupling network which isolates the positive and negative sequence components. This decoupling network gives rise to a new PLL structure which detects the positive sequence voltage component quickly and accurately. In this paper, conclusions of the analytical study are verified by simulation and experiment

关键词： Phase locked loops Voltage control Detectors Power system simulation Control systems Phase detection Frequency Feedback loop Bandwidth Robustness

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Relaxed hierarchical power/ground grid analysis

Relaxed hierarchical power/ground grid analysis

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Asia and South Pacific design Automation Conference

作者： Yici Cai Zhu Pan Xianlong Hong S.X.-D. Tan Wenting Hou Lifeng Wu Department of Computer Science and Technology Tsinghua University Beijing Beijing China Department of Electrical Engineering University of California Riverside Riverside CA USA Cadence Design Systems CA USA

ISBN: (纸本)0780387376

This paper proposes a hierarchical approach to the efficient analysis of large VLSI power/ground grids. Different from the existing hierarchical approach where sub-circuit equivalent models are sparsified with computation-intensive integer programming and the resulting modeling may lead to larger errors if the top circuit matrix has large condition number, the new approach employs an iterative (relaxation) procedure to explicitly compensate the errors and avoid introducing dense matrix caused by the circuit reduction. We also propose an efficient scheme for partitioning high performance center-bumped P/C grids. Experimental results demonstrate that the new algorithm is more accurate than the existing hierarchical method while delivering more speedup over the flat simulators.

关键词： Iterative algorithms Circuit simulation Very large scale integration Iterative methods Partitioning algorithms Admittance Linear programming Programmable control Chip scale packaging Linear circuits

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System-level design: a strategic investment for the future of the electronic industry

System-level design: a strategic investment for the future o...

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International Symposium on VLSI design, Automation and Test

作者： A. Sangiovanni-Vincentelli Cadence Design Systems San Jose USA The Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Science University of California at Berkeley CA USA

A rigorous and well-supported system-level design methodology is essential to solve some of the pressing problems of the electronics. In the electronic system industry (e.g., automotive, consumer, defense, telecommunication), the reduction of the life time of products, the increasing market demands in terms of cost and features, the complexity of the design problem have created problems that are causing severe inefficiencies and may even jeopardize the economic viability of a company. In the semiconductor industry, the deep submicron effects, the increasing manufacturing and NRE costs, make the design of new circuits a very challenging proposition. These combined effects require a novel way of approaching the design problems. We present some issues and potential solutions stressing the strategic nature of system level design. Investing in methodologies, environments and tools for system-level design has to be considered strategic by all players in the electronic industry.

关键词： System-level design Investments Electronics industry Costs Pressing Consumer electronics Communication industry Defense industry Industrial economics Automotive engineering

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Partitioning-based approach to fast on-chip decap budgeting and minimization

Partitioning-based approach to fast on-chip decap budgeting ...

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design Automation Conference

作者： Hang Li Zhenyu Qi S.X.D. Tan Lifeng Wu Yici Cai Xianlong Hong Department of Electrical Engineering University-of California Riverside CA USA Cadence Design Systems Inc. San Jose CA Department of Computer Science and Technology Tsinghua University Beijing China

ISBN: (纸本)1595930582

This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's VLSI physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But it adopts several new techniques, which significantly improve the efficiency of the optimization process. First, the new approach applies the time-domain merged adjoint network method for fast sensitivity calculation. Second, an efficient search step scheme is proposed to replace the time-consuming line search phase in conventional conjugate gradient method for decap budget optimization. Third, instead of optimizing an entire large circuit, we partition the circuit into a number of smaller sub-circuits and optimize them separately by exploiting the locality of adding decaps. Experimental results show that the proposed algorithm achieves at least 10X speed-up over the fastest decap allocation method reported so far with similar or even better budget quality and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations.

关键词： Circuits Partitioning algorithms Optimization methods Capacitance Minimization methods Very large scale integration Algorithm design and analysis Character generation Time domain analysis Gradient methods

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