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IEEE International Symposium on Quality Electronic design

作者： S. Mitra E.J. McCluskey Center For Reliable Computing Computer Systems Laboratory Departments of Electrical Engineering and Computer Science University of Stanford Stanford CA USA

ISBN: (纸本)0769510256

Concurrent error detection (CED) techniques are widely used to ensure data integrity in digital systems. Data integrity guarantees that the system outputs are either correct or an error is indicated when incorrect outputs are produced. This dissertation presents the results of theoretical and simulation studies of various CED techniques. The CED schemes studied are based on diverse duplication, simple duplication of identical implementations, and error-detection techniques like parity checking. The study aimed at [1] a quantitative comparison of the effectiveness different CED schemes, and (2) developing design techniques for efficient concurrent error detection.

关键词： Failure analysis computer errors Concurrent computing Redundancy Laboratories Digital systems Error correction Analytical models Algorithm design and analysis Electromagnetic interference

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Using SAT for combinational equivalence checking 01

Using SAT for combinational equivalence checking

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Proceedings of the conference on design, automation and test in Europe

作者： E. Goldberg M. Prasad R. Brayton Cadence Berkeley Laboratories Cadence Design Systems Department of Electrical Engineering & Computer Sciences University of California Berkeley

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Practical approximation algorithms for separable packing linear programs 7th

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7th International Workshop on Algorithms and Data Structures, WADS 2001

作者： Dragan, Feodor F. Kahng, Andrew B. M Ã Ndoiu, Ion I. Muddu, Sudhakar Zelikovsky, Alexander Department of Computer Science Kent State University KentOH44242 United States Departments of Computer Science and Engineering and of Electrical and Computer Engineering UC San Diego La JollaCA92093-0114 United States Department of Computer Science UC Los Angeles Los AngelesCA90095-1596 United States Sanera Systems Inc Santa ClaraCA United States Department of Computer Science Georgia State University AtlantaGA30303 United States

ISBN: (纸本)3540424237

We describe fully polynomial time approximation schemes for generalized multicommodity flow problems arising in VLSI applications such as Global Routing via Buffer Blocks (GRBB). We extend Fleischer’s improvement [7] of Garg and K¨onemann [8] fully polynomial time approximation scheme for edge capacitated multicommodity flows to multiterminal multicommodity flows in graphs with capacities on vertices and subsets of vertices. In addition, our problem formulations observe upper bounds and parity constraints on the number of vertices on any source-to-sink path. Unlike previous works on the GRBB problem [5,17], our algorithms can take into account (i) multiterminal nets, (ii) simultaneous buffered routing and compaction, and (iii) buffer libraries. Our method outperforms existing algorithms for the problem and has been validated on top-level layouts extracted from a recent high-end microprocessor design. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Approximation algorithms

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A high-speed multi-port data buffer design for low-energy DSP applications

A high-speed multi-port data buffer design for low-energy DS...

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Annual IEEE International ASIC/SOC Conference

作者： Sangjin Hong Shu-Shin Chin Fanshi Zhao Mobile Systems Design Laboratory Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0780367413

Area and power of data storage elements can be excessively large in many data intensive DSP ASICs, such as high-throughput pipelined-FFTs and data interleavers. In this paper, we present a low-complexity multi-port data buffer design methodology based on dynamic memory configuration that results in small area and low power overhead by adapting the buffer architecture to the data access requirements. The buffer minimizes the number of transistors and simplifies-the interface between memory core and external digital circuitry. The buffer can be designed with a low cost digital circuit processing technology. To evaluate our methodology, we designed a buffer for data interleaver and pipelined FFT that requires high throughput. We compare the buffer with conventional buffers based on static memory.

关键词： computer buffers Digital signal processing Application specific integrated circuits Digital circuits design methodology Digital signal processing chips Random access memory Application software Flexible printed circuits Throughput

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Using SAT for combinational equivalence checking

Using SAT for combinational equivalence checking

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design, Automation and Test in Europe Conference and Exhibition

作者： E.I. Goldberg M.R. Prasad R.K. Brayton Cadence Design Systems Cadence Berkeley Laboratories USA Department of Electrical Engineering & Computer Sciences University of California Berkeley USA

ISBN: (纸本)0769509932

This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. A number of recently proposed BDD based approaches have met with considerable success in this area. However, the growing gap between the capability of current solvers and the complexity of verification instances necessitates the exploration of alternative, better solutions. This paper revisits the application of Satisfiability (SAT) algorithms to the combinational equivalence checking (CEC) problem. We argue that SAT is a more robust and flexible engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice. Preliminary results on a simple framework for SAT based CEC show a speedup of up to two orders of magnitude compared to state-of-the-art SAT based methods for CEC and also demonstrate that even with this simple algorithm and untuned prototype implementation it is only moderately slower and sometimes faster than a state-of-the-art BDD based mixed engine commercial CEC tool. While SAT based CEC methods need further research and tuning before they can surpass almost a decade of research in BDD based CEC, the recent progress is very promising and merits continued research.

关键词： Binary decision diagrams Engines Robustness Algorithm design and analysis Laboratories Prototypes Circuit optimization Digital circuits design methodology Digital systems

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Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints 01

Integrated hardware-software co-synthesis for design of embe...

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Proceedings of the conference on design, automation and test in Europe

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York (SUNY) at Stony Brook Stony Brook NY

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Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints

Integrated hardware-software co-synthesis and high-level syn...

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design, Automation and Test in Europe Conference and Exhibition

作者： A. Doboli VLSI Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

ISBN: (纸本)0769509932

This paper presents an integrated approach to hardware software co-synthesis and HLS for design of low-power embedded systems. The main motivation for this work is that fine trade-offs between latency and power can be explored at the system level only with a detailed knowledge of used hardware resources. Integrated method was realized as a simulated annealing based solution-space exploration. Exploration is guided by Performance Models, that exactly capture the relationship between performances i.e. power consumption and latency and design decisions i.e. binding and scheduling. The proposed approach permits nor only a more accurate latency and power estimation but also the exposure of RTL-level design decisions at the system level. As a result, more effective power-latency trade-offs are possible during co-synthesis as compared to traditional task-level methods.

关键词： High level synthesis Embedded system Delay Hardware Power system modeling Energy consumption Very large scale integration Laboratories Embedded software Annealing

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Regular dynamics of low-frequency fluctuations in external cavity semiconductor lasers

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Physical Review E 2001年第5期63卷 056206-056206页

作者： Ruslan L. Davidchack Ying-Cheng Lai Athanasios Gavrielides Vassilios Kovanis Department of Mathematics and Computer Science University of Leicester Leicester LE1 7RH United Kingdom Departments of Mathematics Electrical Engineering and Physics Center for Systems Science and Engineering Arizona State University Tempe Arizona 85287 Nonlinear Optics Group Air Force Research Laboratory DELO Kirtland AFB Albuquerque New Mexico 87117 Department of Electrical and Computer Engineering University of New Mexico Albuquerque New Mexico 87131

It is commonly believed that the dynamics responsible for low-frequency fluctuations (LFF’s) in external cavity semiconductor lasers is stochastic or chaotic. A common approach to address the origin of LFF’s is to investigate the dynamical behavior of, and the interaction among, various external cavity modes in the Lang-Kobayashi (LK) paradigm. In this paper, we propose a framework for understanding of the LFFs based on a different set of fundamental solutions of the LK equations, which are periodic or quasiperiodic, and which are characterized by a sequence of time-locked pulses with slowly varying magnitude. We present numerical evidence and heuristic arguments, indicating that the dynamics of LFF’s emerges as a result of quasiperiodic bifurcations from these solutions as the pumping current increases. Regular periodic solutions can actually be observed when (1) the feedback level is moderate, (2) pumping current is below solitary threshold, and (3) the linewidth enhancement factor is relatively large.

关键词： Semiconductor lasers

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Feedforward and deterministic fuzzy control of balance and posture during human gait

Feedforward and deterministic fuzzy control of balance and p...

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IEEE International Conference on Robotics and Automation (ICRA)

作者： E. Kubica D. Wang D. Winter Department of Systems Design Engineering University of Waterloo Waterloo ONT Canada Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada Department of Kinesiology University of Waterloo Waterloo ONT Canada

ISBN: (纸本)0780365763

The primary objective of this research is to model the biomechanical control system employed by the central nervous system (CNS) to maintain posture and balance of the head-arms-torso (HAT) during gait. More specifically, the intent is to stabilize a model of the upper body so that the HAT response is similar to that found experimentally in human subjects during gait. This is accomplished by using appropriate physiological parameters as feedback to generate realistic control signals at the hip musculature. The modelling includes the HAT musculoskeletal characteristics as well as pure neural time delays. The CNS control system is modelled by a linear state feedback controller as well as a hybrid fuzzy controller that has been adapted from a linear quadratic regulator. In addition, a newly derived feedforward component is demonstrated. It is expected that a better understanding of the human fait process will prove valuable in designing assistive devices and bipedal robots.

关键词： Fuzzy control Humans Biological system modeling Linear feedback control systems Control system synthesis Centralized control Central nervous system Neurofeedback Signal generators Hip

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Error analysis for time-interleaved analog channels

Error analysis for time-interleaved analog channels

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Baiying Yu W.C. Black Agere Systems Allentown PA USA Analog and Mixed-Signal Design Center Department of Electrical and Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)0780366859

Time-interleaved architectures are frequently employed in high-speed data converters and signal processing channels in order to achieve the highest possible speed. However, the performance of the combined channels is reduced if each channel is not well matched in terms of gain, converter offset and timing skew. In this paper, the errors introduced by gain and offset mismatch and timing skew is analyzed in detail. The digital spectra due to mismatch between channels is derived by applying digital signal processing theories and the closed-forms of signal-to-noise ratio (SNR) are derived and verified using Matlab/sup TM/.

关键词： Error analysis Timing Signal to noise ratio Clocks Sampling methods Signal processing Performance gain computer languages Equations Signal design

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