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International Conference on Parallel Processing (ICPP)

作者： V. Kim P. Banerjee K. De Department of Electrical & Computer Engineering Northwestern University Evanston IL USA Ambit Group Cadence Design Systems San Jose CA USA

We present a fine-grained parallel processing scheme for speeding up an industrial VLSI synthesis tool on a network of workstations without sacrificing the quality of results. The synthesis tool is Ambit BuildGates, a high-capacity ASIC logic synthesis software from Cadence design systems. We examine some necessary operating conditions for a practical parallel implementation of such a software, and propose a parallel approach which accommodates for the highly-irregular computation requirements in synthesis and the high-latency, low-bandwidth conditions of the target environment. For pragmatic as well as performance concerns, we designed a parallel algorithm which produces results (synthesized logic) that are identical to those of the original uniprocessor algorithm. We employ heuristic load assessment and adaptive cyclic distribution in order to actively balance the unpredictable load throughout execution, which enables a considerable reduction in runtime (i.e. 51.3 hours down to 23.4 hours) on actual customer design benchmarks.

关键词： Very large scale integration Network synthesis Logic design design automation Parallel processing Workstations Application specific integrated circuits Software tools Software design Concurrent computing

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A BDD-based satisfiability infrastructure using the unate recursive paradigm

A BDD-based satisfiability infrastructure using the unate re...

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design, Automation and Test in Europe Conference and Exhibition

作者： P. Kalla Zhihong Zeng M.J. Ciesielski Chilai Huang Department of Electrical and Computer Engineering University of Massachusetts Amherst Amherst MA USA Avery Design Systems Inc. Andover MA USA

Binary Decision Diagrams have been widely used to solve the Boolean satisfiability (SAT) problem. The individual constraints can be represented using BDDs and the conjunction of all constraints provides all satisfying solutions. However, BDD-related SAT techniques suffer from size explosion problems. This paper presents two BDD-based algorithms to solve the SAT problem that attempt to contain the growth of BDD-size while identifying solutions quickly. The first algorithm, called BSAT, is a recursive, backtracking algorithm that uses an exhaustive search to find a SAT solution. The well known unate recursive paradigm is exploited to solve the SAT problem. The second algorithm is exploited to solve the SAT problem. The second algorithm, called INCOMPLETE-SEARCH-USAT (abbreviated IS-USAT), incorporates an incomplete search to find a solution. The search is incomplete inasmuch as it is restricted to only those regions that have a high likelihood of containing the solution, discarding the rest. Using our techniques we were able to find SAT solutions not only for all MCNC&ISCAS benchmarks, but also for a variety of industry standard designs.

关键词： Data structures Boolean functions Binary decision diagrams Circuits Read only memory Iterative algorithms Automatic test pattern generation Engines Testing

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A BDD-based satisfiability infrastructure using the unate recursive paradigm 00

A BDD-based satisfiability infrastructure using the unate re...

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design, Automation and Test in Europe Conference and Exhibition

作者： Priyank Kalla Zhihong Zeng Maciej J. Ciesielski Chilai Huang Department of Electrical and Computer Engineering University of Massachusetts at Amherst Amherst MA Avery Design Systems Inc. 2 Atwood Lane Andover MA

ISBN: (纸本)0769505376

Binary Decision Diagrams have been widely used to solve the Boolean Satisfiability (SAT)problem. The individual constraints can be represented using BDDs and the conjunction of all constraints provides all satisfying solutions. However BDD-related SAT techniques suffer from size explosion problems. This paper presents two BDD-based algorithms to solve the SAT problem that attempt to contain the growth of BDD-size while identifying solutions quickly. The first algorithm, called BSAT is a recursive, backtracking algorithm that uses an exhaustive search to find a SAT solution. The well known unate recursive paradigm is exploited to solve the SAT problem. The second algorithm, called INCOMPLETE-SEARCH-USAT (abbreviated IS-USAT), incorporates an incomplete search to find a solution. The search is incomplete inasmuch as it is restricted to only those regions that have a high likelihood of containing the solution, discarding the rest. Using our techniques we were able to find SAT solutions not only for all MCNC & ISCAS benchmarks, but also for a variety of industry standard designs.

关键词： SEMI-AUTOMATIC TRIM College Entrance Examination Board Scholastic Aptitude Test Binary decision diagrams Recursive computability exhaustive search Solutions decision diagrams Solve

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Incremental CAD

Incremental CAD

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IEEE International Conference on computer-Aided design

作者： O. Coudert J. Cong S. Malik M. Sarrafzadeh Monterey Design Systems Sunnyvale CA USA Computer Science Department University of California Los Angeles CA USA Department of Electrical Engineering Princeton University Princeton NJ USA Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

Comprehensive study of incremental algorithms and solutions in the context of CAD tool development is an open area of research with a great deal of potential. Incremental algorithms for synthesis and layout are needed when design undergoes local or incremental change. Often these local changes are made to react to local change in the design, correct local errors or to make local improvements in one or more of the design quality metrics. In this paper we outline fundamental problems in incremental logic synthesis and physical design. Preliminary solutions to a subset of these problems are outlined.

关键词： Iterative algorithms design automation Routing Timing Very large scale integration Logic Algorithm design and analysis Error correction Crosstalk Field programmable gate arrays

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A maintainability model for industrial software systems using design level metrics

A maintainability model for industrial software systems usin...

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Working Conference on Reverse engineering

作者： S. Muthanna K. Kontogiannis K. Ponnambalam B. Stacey Department of Electrical & Computer Engineering University of Waterloo Waterloo ONT Canada Nortel SEAL Laboratory University of Waterloo Ottawa Canada Department of Systems Design Engineering University of Waterloo Waterloo ONT Canada

ISBN: (纸本)0769508812

Software maintenance is a time consuming and expensive phase of a software product's life-cycle. The paper investigates the use of software design metrics to statistically estimate the maintainability of large software systems, and to identify error prone modules. A methodology for assessing, evaluating and, selecting software metrics for predicting software maintainability is presented. In addition, a linear prediction model based on a minimal set of design level software metrics is proposed. The model is evaluated by applying it to industrial software systems.

关键词： computer industry Software systems Software design Software maintenance Software metrics Software quality Maintenance engineering design engineering Seals Predictive models

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Guest Editorial

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Intelligent Automation & Soft Computing 2000年第3期6卷 171-172页

作者： Mohamed Kamel[a] & Mohammad Jamshidi[b] [a] Pattern Analysis and Machine Intelligence Lab Department of Systems Design Engineering University of Waterloo Waterloo Ontario N2L 3G1 Canada [b] Nasa Center for Autonomous Control Engineering and Department of Electrical and Computer Engineering The University of New Mexico Albuquerque NM 87131 USA http://ace.tmm.edu

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Measuring, modeling and decoupling of saturation-induced saliencies in carrier signal injection-based sensorless AC drives

Measuring, modeling and decoupling of saturation-induced sal...

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Conference Record of the IEEE Industry Applications Society Annual Meeting (IAS)

作者： F. Briz M.W. Degner A. Diez R.D. Lorenz Department of Electrical Computer & Systems Engineering University of Oviedo Gijon Spain Scientific Research Laboratory Ford Motor Company Limited Dearborn MI USA Departments of ME & ECE University of Wisconsin Madison Madison WI USA

The focus of this paper is the measuring, modeling, and decoupling of saturation-induced saliencies in carrier signal injection based sensorless control. First techniques for the measurement of saturation-induced saliencies are presented. The goal of these measurements is to provide useful information on the position and magnitude of the various saturation-induced saliencies. Using the results from several different experimental measurements, models are developed explaining the source and behavior of the saturation-induced saliencies. The paper concludes by presenting methods for decoupling the effects caused by the parasitic saturation-induced saliencies, eliminating the errors that they cause in rotor position or flux angle estimation.

关键词： Rotors Frequency Inductance Position measurement Bars Estimation error Torque Stators systems engineering and theory Laboratories

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Study of a Cr doped TiO/sub 2/ derived from sol-gel process for gas sensing

Study of a Cr doped TiO/sub 2/ derived from sol-gel process ...

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Conference on Optoelectronic and Microelectronic Materials and Devices

作者： J.M. Booth L. Nguyen C.J. Rix D.E. Mainwaring Y.X. Li W. Wlodarski S.H. Moslih S.P. Russo School of Electrical & Computer Systems Engineering RMIT University Melbourne Australia Departments of Appl. Chem. R. Melbourne Inst. of Technol. Vic. Australia Applied Physics RMIT University Melbourne Australia Department of Applied Chemistry RMIT University Melbourne Australia

ISBN: (纸本)0780366980

The sol-gel route to thin bimetallic oxide sensor films was studied in terms of the evolution of a viscoelastic Ti gel precursor containing occluded Cr. The influence of Cr:Ti atomic ratio and annealing temperature was related to the resultant microstructure, morphology and oxygen sensing response of the annealed thin films. It was shown that progressive increase in Cr content changed the Ti-O properties from a n-type to a p-type semiconductor film with a commensurate reversal in sensor response.

关键词： Chromium Temperature sensors Thin film sensors Annealing Viscosity Elasticity Microstructure Morphology Semiconductor thin films Semiconductor films

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Efficient decision procedures for model checking of linear time logic properties 11th

Efficient decision procedures for model checking of linear t...

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11th International Conference on computer Aided Verification, CAV 1999

作者： Bloem, Roderick Ravi, Kavita Somenzi, Fabio Department of Electrical and Computer Engineering University of Colorado BoulderCO80309-0425 United States Cadence Design Systems New ProvidenceNJ07974-1143 United States

ISBN: (纸本)3540662022

We propose an algorithm for LTL model checking based on the classification of the automata and on guided symbolic search. Like most current methods for LTL model checking, our algorithm starts with a tableau construction and uses a model checker for CTL with fairness constraints to prove the existence of fair paths. However, we classify the tableaux according to their structure, and use efficient decision procedures for each class. Guided search applies hints to constrain the transition relation during fixpoint computations. Each fixpoint is thus translated into a sequence of fixpoints that are often much easier to compute than the original one. Our preliminary experimental results suggest that the new algorithm for LTL is quite efficient. In fact, for properties that can be expressed in both CTL and LTL, the algorithm is competitive with the CTL model checking algorithm. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Model checking

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Extracting Java library subsets for deployment on embedded systems

Extracting Java library subsets for deployment on embedded s...

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(CSMR) European Conference on Software Maintenance and Reengineering

作者： D. Rayside K. Kontogiannis Systems Design Engineering University of Waterloo Canada Electrical & Computer Engineering University of Waterloo Canada

Embedded systems provide means for enhancing the functionality delivered by small-sized electronic devices such as hand-held computers and cellular phones. Java is a programming language which incorporates a number of features that are useful for developing such embedded systems. However the size and the complexity of the Java language and its libraries have slowed its adoption for embedded systems, due to the processing power and storage space limitations found in these systems. A common approach to address storage space limitations is for the vendor to offer special versions of the libraries with reduced functionality and size to meet the constraints of embedded systems. This paper presents a technique that is used for dynamically selecting, on an as needed basis, the subset of library entities that is exactly required for a given Java application to run. This subset can then be down-loaded to the device for execution. The advantage of this approach is that the developer can use arbitrary libraries, instead of being restricted to those which have been adapted for embedded systems by the vendors. A prototype system, that dynamically builds library subsets on an as needed per application basis, has been built and tested on several mid-size Java applications with positive results.

关键词： Java Libraries Embedded system design engineering Embedded computing Handheld computers systems engineering and theory computer languages Electronic switching systems Prototypes

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