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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： J. Pou P. Rodriguez J. Zaragoza V. Sala C. Jaen D. Boroyevich Departments of Electronic and Electrical Engineering Power Quality and Renewable Energy (QuPER) Research Group Technical University of Catalonia Spain Departments of Electronic and Electrical Engineering Research Group Terrassa Catalonia SPAIN Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Virginia Polytechnic Institute and State University Blacksburg VA USA Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Blacksburg VA USA

Carrier-based modulation strategies can be improved by inclusion of zero sequences in the modulation signals. In this paper, the modulation signals of a three-level neutral-point-clamped converter are modified to achieve maximum benefit of the DC-link voltage, and to help achieve voltage balance between the DC-link capacitors. The proposed strategy is obtained from the analysis of space-vector modulation patterns. Therefore, compared to standard sinusoidal PWM, 15% larger amplitudes of the output voltage fundamentals, better voltage-balancing performance, and lower switching frequencies in the devices can all be achieved. Furthermore, implementation of this modulation technique in a digital-signal processor is much easier than space-vector modulation, and also lowers processing time requirements. Efficiency of the modulation algorithm is verified by simulation and experiment

关键词： Voltage Pulse width modulation Support vector machines Capacitors Digital modulation Pulse width modulation converters Pattern analysis Switching frequency Sampling methods Field programmable gate arrays

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Automatic selection of DBS target points using multiple electrophysiological atlases

Automatic selection of DBS target points using multiple elec...

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8th International Conference on Medical Image Computing and computer-Assisted Intervention - MICCAI 2005

作者： D'Haese, Pierre-Francois Pallavaram, Srivatsan Niermann, Ken Spooner, John Kao, Chris Konrad, Peter E. Dawant, Benoit M. Department of Electrical Engineering and Computer Science Vanderbilt University Nashville TN United States Université Catholique de Louvain Louvain-la-Neuve Belgium Departments of Neurosurgery Vanderbilt Medical Center Nashville TN United States Departments of Radiology Vanderbilt Medical Center Nashville TN United States Sentient Medical Systems Cockeysville MD 21030

ISBN: (纸本)3540293264

In this paper we study and evaluate the influence of the choice of a particular reference volume as the electrophysiological atlas on the accuracy of the automatic predictions of optimal points for deep brain stimulator (DBS) implants. We refer to an electrophysiological atlas as a spatial map of electrophysiological information such as micro electrode recordings (MER), stimulation parameters, final implants positions, etc., which are acquired for each patient and then mapped onto a single reference volume using registration algorithms. An atlas-based prediction of the optimal point for a DBS surgery is made by registering a patient's image volume to that reference volume, that is, by computing a correct coordinate mapping between the two;and then by projecting the optimal point from the atlas to the patient using the transformation from the registration algorithm. Different atlases, as well as different parameterizations of the registration algorithm, lead to different and somewhat independent atlas-based predictions. We show how the use of multiple reference volumes can improve the accuracy of prediction by combining the predictions from the multiple reference volumes weighted by the accuracy of the non-rigid registration between each of the corresponding atlases and the patient volume. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Medical imaging

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Equalizing data-path for processing speed determination in block level pipelining

Equalizing data-path for processing speed determination in b...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present, in this paper, a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.

关键词： Pipeline processing Communication system control Signal processing algorithms Control systems Hardware Centralized control Frequency synchronization Distributed control Mobile computing Laboratories

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AES crypto chip utilizing high-speed parallel pipelined architecture

AES crypto chip utilizing high-speed parallel pipelined arch...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： D. Kotturi Seong-Moo Yoo J. Blizzard Cadence Design Systems Plano TX USA Electrical and Computer Engineering Dept University of Alabama Huntsville Huntsville AL USA

In November 2001, the National Institute of Standards and Technology (NIST) of the USA chose the Rijndael algorithm as the suitable Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) algorithm. Since then, many hardware implementations have been proposed in literature. We present a hardware-efficient design increasing throughput for the AES algorithm using a high-speed parallel pipelined architecture. By using an efficient inter-round and intra-round pipeline design, our implementation achieves a high throughput of 29.77 Gbit/s in encryption whereas the highest throughput reported in the literature is 21.54 Gbit/s.

关键词： Cryptography Throughput Algorithm design and analysis NIST Hardware Data security National security computer architecture Pipeline processing Field programmable gate arrays

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Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Dynamic coarse grain dataflow reconfiguration technique for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

关键词： Real time systems Switches Integrated circuit interconnections computer architecture Pipeline processing Reconfigurable architectures design methodology Throughput Digital signal processing Parallel processing

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Efficient Space-Vector Modulation Algorithm for Multilevel Converters with Low Switching Frequencies in the Devices

Efficient Space-Vector Modulation Algorithm for Multilevel C...

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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： J. Pou P. Rodriguez D. Boroyevich R. Pindado I. Candela Departments of Electronic and Electrical Engineering Technical University of Catalonia Terrassa Spain Department of Electrical and Computer Engineering Center for Power Electronics Systems (CPES) Virginia Polytechnic Institute and State University Blacksburg VA USA

This paper presents a novel space-vector modulation scheme that can be processed quickly by a digital-signal processor, in addition to achieving minimum switching frequencies in the devices of the converter. The modulation algorithm takes advantage of symmetry in the space-vector diagram to process all the calculations within the first sextant. An equivalent reference vector in this sextant is used for the calculation of duty cycles and the definition of optimal sequences of vectors. By simply interchanging the final states of the legs of the inverter of this equivalent vector generates the original reference vector in the corresponding sextant. The total number of switching steps in the final sequences is preserved; thus, optimal sequences of vectors need only be defined in the first sextant. This strategy is especially attractive for multilevel converters in which the total number of vectors and sequences is very high. Furthermore, since multilevel converters are usually applied to high-power systems, reducing the switching frequencies of the devices is an important goal. Efficiency of the modulation algorithm is verified in the three-level converter by simulation and experiment

关键词： Switching converters Frequency conversion Switching frequency Pulse width modulation inverters Pulse width modulation Digital modulation Digital-to-frequency converters Leg Support vector machines Algorithm design and analysis

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Robust multiscale triangle-area representation for 2D shapes

Robust multiscale triangle-area representation for 2D shapes

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IEEE International Conference on Image Processing

作者： I. El Rube N. Alajlan M. Kamel M. Ahmed G. Freeman Systems Design Engineering University of Waterloo Waterloo ONT Canada Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada Physics and Computer Science Department Wilfrid Laurier University Waterloo ONT Canada

In this paper, a new 2D shape multiscale triangle-area representation (MTAR) is proposed. This representation utilizes a simple geometric principle, the area of a triangle, in obtaining a robust and efficient shape representation. The use of the wavelet transform for decomposing the boundary of the shapes improves the efficiency and robustness of the representation. The MTAR is more robust to the affine transformation, less affected by noise, and more selective than similar methods, e.g., the curvature scale-space CSS. Two tests, using MPEG-7 CE-shape-1 database, show that MTAR achieves better performance than the CSS under affine transformation and in the general shape retrieval.

关键词： Shape Cascading style sheets Noise robustness design engineering Noise shaping MPEG 7 Standard Robust stability Image segmentation Smoothing methods systems engineering and theory

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Comment on “Inability of Lyapunov Exponents to Predict Epileptic Seizures”

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Physical Review Letters 2005年第1期94卷 019801-019801页

作者： Leonidas D. Iasemidis Konstantinos Tsakalis J. Chris Sackellares Panos M. Pardalos The Harrington Department of Bioengineering Arizona State University Tempe Arizona 85287 USA Department of Electrical Engineering Arizona State University Tempe Arizona 85287 USA Departments of Neurology Neuroscience Pediatrics Psychiatry and Biomedical Engineering University of Florida Gainesville Florida 32611 USA Departments of Industrial and Systems Engineering Computer Science and Biomedical Engineering University of Florida Gainesville Florida 32611 USA

A Comment on the Letter by Ying-Cheng Lai et al., Phys. Rev. Lett. 91, 068102 (2003). The authors of the Letter offer a Reply.

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