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Corrigendum to “An extended Attribute-based access control with controlled delegation in IoT” [Journal of Information Systems and Applications 76 (2023) 103473]

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Journal of Information Security and Applications 2024年 83卷

作者： Saher Tegane Khaled Hamouid Mawloud Omar Fouzi Semchedine Abdelmalek Boudries Faculty of Exact Sciences Bejaia University Algeria LIGM ESIEE Paris Université Gustave Eiffel Noisy-le-Grand France INZU - Opportunistic computing and networking for secure and dependable applications IRISA Université Bretagne Sud France Institute of Optics and Precision Mechanics Ferhat Abbas University Setif Algeria Laboratory LMA Commercial Science Dept Faculty of Economics Business & Management Bejaia University Bejaia Algeria

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Corrigendum to “An extended Attribute-based access control with controlled delegation in IoT” [Journal of Information Systems and Applications 76 (2023) 103473]

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Journal of Information Security and Applications 2024年 82卷

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Distributed multi-agent optimization subject to nonidentical constraints and communication delays

Distributed multi-agent optimization subject to nonidentical...

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作者： Lin, Peng Ren, Wei Song, Yongduan School of Electronic and Information Engineering Xi'An Jiaotong University China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China Department of Electrical and Computer Engineering University of California Riverside United States Key Laboratory of Dependable Service Computing Cyber Physical Society Ministry of Education Chongqing University China School of Automation Chongqing University China

In this paper, we study a distributed optimization problem using a subgradient projection algorithm for multi-agent systems subject to nonidentical constraints and communication delays under local communication. Here the agents capable of communicating with their local neighbors are constrained to remain in possibly different closed convex sets and optimize a global objective function composed of a sum of local objective functions, each of which is known to only one agent. First, we consider the case of fixed graphs and show that distributed optimization might not be achieved on general strongly connected directed graphs. Instead, the agents optimize a weighted sum of the local objective functions. Then we consider the case of switching graphs and show that distributed optimization can be achieved when the adjacency matrices are doubly stochastic and the union of the directed graphs is strongly connected among each time interval of a certain bounded length. Furthermore, we consider the case of communication delays, where the delays are mutually independent. It is shown that the distributed optimization problem can be solved by introducing additional delays to the subgradient projection algorithm and the communication delays can be arbitrarily bounded. Finally, numerical examples are included to show the obtained theoretical results. © 2015 Elsevier Ltd. All rights reserved.

关键词： Multi agent systems

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Efficient protection and grooming architectures for future optical networks

Efficient protection and grooming architectures for future o...

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Network Architectures, Management, and Applications VII

作者： Somani, Arun K. Dependable Computing and Networking Laboratory Department of Electrical and Computer Engineering Iowa State University Ames IA 50011 United States

ISBN: (纸本)9780819480354

Today networks are too cumbersome due to the incoherent integration of various technologies developed over time. Convergence of data, voice and video has caused the retro-fitting of a network to support non-native traffic types and this has led to sub-par performance for every traffic type. Fundamental changes are warranted to support high bandwidth traffic. The network must guarantee end-to-end delivery and provide inherent protection within the physical structure. We propose that the main traffic types of today's applications should be carried using the following features: connection-oriented service, traffic grooming to fill those connection oriented pipes, and forward error recovery with protection provided in the physical, layer. We present some of our research results. © 2009 SPIE-OSA-IEEE.

关键词： Network architecture

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Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems

Low overhead Soft Error Mitigation techniques for high-perfo...

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International Conference on dependable Systems and Networks (DSN)

作者： Naga Durga Prasad Avirneni Viswanathan Subramanian Arun K. Somani Dependable Computing and Networking Laboratory Iowa State University Ames IA USA

The threat of soft error induced system failure in high performance computing systems has become more prominent, as we adopt ultra-deep submicron process technologies. In this paper, we propose two techniques, namely soft error mitigation (SEM) and soft and timing error mitigation (STEM), for protecting combinational logic blocks from soft errors. Our first technique (SEM), based on distributed and temporal voting of three registers, unloads the soft error detection overhead from the critical path of the systems. Our second technique (STEM) adds timing error detection capability to guarantee reliable execution in aggressively clocked designs that enhance system performance by operating beyond worst-case clock frequency. We also present a specialized low overhead clock generation scheme that ably supports our proposed techniques. Timing annotated gate level simulations, using 45 nm libraries, of a pipelined adder-multiplier and DLX processor show that both our techniques achieve near 100% fault coverage. For DLX processor, even under severe fault injection campaigns, SEM achieves an average performance improvement of 26.58% over a conventional triple modular redundancy voter based soft error mitigation scheme, while STEM outperforms SEM by 27.42%.

关键词： Timing Clocks High performance computing Protection Logic Voting System performance Frequency Libraries Redundancy

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Managing the Impact of On-chip Temperature on the Lifetime Reliability of Reliably Overclocked Systems

Managing the Impact of On-chip Temperature on the Lifetime R...

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International Conference on Dependability, DEPEND

作者： Viswanathan Subramanian Prem Kumar Ramesh Arun K. Somani Dependable Computing and Networking Laboratory Iowa State University Ames IA USA

Physical and environmental variations require the addition of safety margins to the clock frequency of digital systems, making it overly conservative. Aggressive, but reliable, dynamic clock frequency tuning mechanisms that achieve higher system performance, by adapting the clock rates beyond worst case limits, have been proposed earlier. Even though reliable over-clocking guarantees functional correctness, it leads to higher power consumption and overheating. As a consequence, reliable over-clocking without considering on-chip temperatures will bring down the lifetime reliability of the chip. In this paper, we analyze how reliable over-clocking impacts the on-chip temperature of microprocessors, and evaluate the effects of overheating, due to reliable dynamic over-clocking mechanisms, on the lifetime reliability of such systems. We, then, evaluate the effects of performing thermal throttling, a technique that clamps the on-chip temperature below a predefined value, on system performance and reliability. Our study shows that a reliably over-clocked system, along with dynamic thermal throttling, achieves around 25% performance improvement, while operating within 355 K.

关键词： System-on-a-chip Temperature Power system reliability Clocks Frequency System performance Safety Digital systems Tuning Energy consumption

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Efficient protection and grooming architectures for future optical networks

Efficient protection and grooming architectures for future o...

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Asia Communications and Photonics Conference and Exhibition (ACP)

作者： Arun K. Somani Dependable Computing & Networking Laboratory Department of Electrical & Computer Engineering Iowa State University Ames IA USA

Today networks are too cumbersome due to the incoherent integration of various technologies developed over time. Convergence of data, voice, and video has caused the retro-fitting of a network to support non-native traffic types and this has led to sub-par performance for every traffic type. Fundamental changes are warranted to support high bandwidth traffic. The network must guarantee end-to-end delivery and provide inherent protection within the physical structure. We propose that the main traffic types of today's applications should be carried using the following features: connection-oriented service, traffic grooming to fill those connection oriented pipes, and forward error recovery with protection provided in the physical layer. We present some of our research results.

关键词： Protection Optical fiber networks Telecommunication traffic Wavelength division multiplexing Optical packet switching WDM networks Bandwidth SONET Peer to peer computing Packet switching

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Conjoined pipeline: Enhancing hardware reliability and performance through organized pipeline redundancy

Conjoined pipeline: Enhancing hardware reliability and perfo...

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14th IEEE Pacific Rim International Symposium on dependable computing, PRDC 2008

作者： Subramanian, Viswanathan Somani, Arun K. Dependable Computing and Networking Laboratory Iowa State University Ames IA United States

ISBN: (纸本)9780769534480

Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree of fault tolerance and enhances performance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing its output to the replicated pipeline registers. The organization of redundancy in the proposed Conjoined Pipeline system supports overclocking, provides concurrent error detection and recovery capability for soft errors, intermittent faults and timing errors, and flags permanent silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Back annotated post-layout gate level timing simulations, using 45nm technology, of a conjoined two stage arithmetic pipeline and a conjoined five stage DLX pipeline processor, with forwarding logic, show that our approach achieves near 100% fault coverage, under a severe fault injection campaign, while enhancing performance, on an average by about 20%, when dynamically overclocked and 35%, when maximally overclocked. © 2008 IEEE.

关键词： Redundancy

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Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy

Conjoined Pipeline: Enhancing Hardware Reliability and Perfo...

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Pacific Rim International Symposium on dependable computing

作者： Viswanathan Subramanian Arun K. Somani Dependable Computing and Networking Laboratory Iowa State University Ames IA USA

Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree of fault tolerance and enhances performance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing its output to the replicated pipeline registers. The organization of redundancy in the proposed conjoined pipeline system supports overclocking, provides concurrent error detection and recovery capability for soft errors, intermittent faults and timing errors, and flags permanent silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Back annotated post-layout gate level timing simulations, using 45 nm technology, of a conjoined two stage arithmetic pipeline and a conjoined five stage DLX pipeline processor, with forwarding logic, show that our approach achieves near 100% fault coverage, under a severe fault injection campaign, while enhancing performance, on an average by about 20%, when dynamically overclocked and 35%, when maximally overclocked.

关键词： Pipelines Hardware Redundancy Logic Timing Organizing Fault tolerance Writing Fault detection Silicon

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Superscalar Processor Performance Enhancement Through Reliable Dynamic Clock Frequency Tuning

Superscalar Processor Performance Enhancement Through Reliab...

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Annual IEEE/IFIP International Conference on dependable Systems and Networks

作者： Viswanathan Subramanian Mikel Bezdek Naga D. Avirneni Arun Somani Dependable Computing and Networking Laboratory Iowa State University Ames IA USA

ISBN: (纸本)9781424430826

Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, this has special implications since the operating frequency of the entire pipeline is limited by the slowest stage. Our goal, in this paper, is to achieve higher performance in superscalar processors by dynamically varying the operating frequency during run time past worst case limits. The key objective is to see the effect of overclocking on superscalar processors for various benchmark applications, and analyze the associated overhead, in terms of extra hardware and error recovery penalty, when the clock frequency is adjusted dynamically. We tolerate timing errors occurring at speeds higher than what the circuit is designed to operate at by implementing an efficient error detection and recovery mechanism. We also study the limitations imposed by minimum path constraints on our technique. Experimental results show that an average performance gain up to 57% across all benchmark applications is achievable.

关键词： Superscalar processor Dynamic overclocking Fault-Tolerant computing Reliability

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