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Code positioning for VLIW architectures 9th

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9th International Conference on High-Performance Computing and Networking, HPCN Europe 2001

作者： Cilio, Andrea G. M. Corporaal, Henk Delft University of Technology Computer Architecture and Digital Techniques Dept Mekelweg 4 Delft2628CD Netherlands

ISBN: (纸本)3540422935

Several studies have considered reducing instruction cache misses and branch penalty stall cycles by means of various forms of code placement. Most proposed approaches rearrange procedures or basic blocks in order to speed up execution on sequential architectures with branch prediction. Moreover, most works focus mainly on instruction cache performance and disregard execution cycles. To the best of our knowledge, no work has specifically addressed statically scheduled ILP machines like VLIWs, with control-transfer delay slots. We propose a new code positioning algorithm especially designed for VLIW-style architectures, which allows to trade off tighter schedule for program locality. Our measurements indicate that code positioning, as a result of tighter program schedule and removed unconditional jumps, can significantly reduce the number of execution cycles, by up to 21%, while improving program locality and instruction cache performance. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Very long instruction word architecture

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Tuning buffer size in the multimedia router (MMR) 15

Tuning buffer size in the multimedia router (MMR)

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15th International Parallel and Distributed Processing Symposium, IPDPS 2001

作者： Caminero, B. Carrión, C. Quiles, F.J. Duato, F.J. Yalamanchili, S. Dept. of Computer Science Escuela Politecnica Superior Univ. de Castilla-La Mancha Albacete02071 Spain Dept. of Information Systems and Computer Architecture Univ. Politecnica de Valencia Valencia46071 Spain School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332-0250 United States

ISBN: (纸本)0769509908

The primary objective of the Multimedia Router (MMR) project is the design and implementation of a compact router optimized or multimedia applications. The router is targeted for use in cluster and LAN interconnection networks, which offer different constraints and therefore differing router solutions than WANs. One of the key design parameters is the amount of buffer space, which is closely related to the silicon area required to implement the router. In this paper, the MMR performance obtained when varying the size of the input buffers is explored. Preliminary results show that buffers as small as one flit large suffice to guarantee QoS to both CBR and VBR traffic, thanks to the use of flow control and short links. © 2001 IEEE.

关键词： Interconnection networks (circuit switching)

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Effectiveness of neural network and genetic algorithm in hull form design

Effectiveness of neural network and genetic algorithm in hul...

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ASME 2001 International Design Engineering Technical Conferences and computers and Information in Engineering Conference, IDETC-CIE 2001

作者： Khondoker, M. Reaz H. Rahman, Chowdhury Mofizur Islam, Mohammad Mahfuzul Dept. of Naval Architecture and Marine Engineering United States Dept. of Computer Science and Engineering Bangladesh University of Engineering and Technology Dhaka1000 Bangladesh

This paper aims at developing a fully automated hull form design technique employing an Neural Network and Genetic Algorithm methods resulting in accelerated convergence. For generating an input data that will be, by and large, a close relative of the desired hull, a linear relation has been assumed between the half breadth of different sections and principal dimensions (length, breadth, draft or (displacement)13) of a particular type of vessel. Compared to starting with a random value of the input, this technique resulted in faster convergence. The weight matrix for each of these parameters is produced from data obtained from the population. The half-breadth table for a new vessel can be obtained by multiplying the weight matrix with corresponding parameter. However, the half-breadth table obtained in such way may not provide the required displacement and speed of the vessel. Therefore, some readjustments of some of the principal dimensions are required. Neural Networks (Wasserman, 1989) has been used to find the required values of such improved design parameters (principal dimensions). The final design process consists of searching for the exact solution by examining several generations generated by the GA (Goldberg, 1989). The convergence criterion is the summed offset error, which is to be within the envelope defined by the tolerances. Since GA doesn't guarantee fairness of the surface of the hull form, B-spline curve fitting method is used to obtain a fair hull. Thus, the hull form generated through this process is fully automated, accurate and having fair surface. The technique is also found to be an efficient one. Copyright © 2001 by ASmE.

关键词： Design

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A network-computing infrastructure for tool experimentation applied to computer architecture education

A network-computing infrastructure for tool experimentation ...

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2000 Workshop on computer architecture Education, WCAE 2000

作者： Figueiredo, Renato J. Fortes, José A. B. Eigenmann, Rudolf Kapadia, Nirav Adabala, Sumalatha Miguel-Alonso, Jose Taylor, Valerie Livny, Miron Vidal, Luis Chen, Jan-Jo School of ECE Purdue University United States Department of EECS Northwestern University United States Dept. of Mathematics and Computer Science Chicago State University United States Dept. of Computer Architecture and Technology University of the Basque Country Spain Computer Sciences Department University of Wisconsin-Madison United States

ISBN: (纸本)9781450347303

computer architects increasingly depend on the use of software tools to evaluate and investigate the design of computer systems. It is therefore very important that educators in this field promote extensive tool-based student experimentation in architecture classes. However, the integration of today's complex architecture tools into curricula poses several challenges to an instructor, including management of powerful computing resources, software installation and maintenance, and development of tool-specific educational material. This paper describes how these challenges are addressed by a universally accessible network-computing infrastructure - NETCARE - that provides educators with a Web portal to access computing resources, executable tools and educational material. Copyright held by author.

关键词： Portals

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Floating point to fixed point conversion of C code 8th

Floating point to fixed point conversion of C code

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8th International Conference on Compiler Construction, CC 1999 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 1999

作者： Cilio, Andrea G M Corporaal, Henk Delft University of Technology Computer Architecture and Digital Techniques Dept. Mekelweg 4 Delft2628CD Netherlands

ISBN: (纸本)3540657177

In processors that do not support floating-point instructions, using fixed-point arithmetic instead of floating-point emulation trades off computation accuracy for execution speed. This trade-off is often profitable. In many cases, like embedded systems, low-cost and speed bounds make it the only acceptable option. We present an environment supporting fixed-point code generation from C programs. It allows the user to specify the position of the binary point in the source code and let the converter automatically transform floating-point variables and operations. We demonstrate the validity of our approach on a series of experiments. The results show that, compared to floating-point, fixedpoint arithmetic executed on an integer datapath has a limited impact on the accuracy. In the same time the fixed-point code is 3 to 8 times faster than its equivalent floating-point emulation on an integer datapath. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Fixed point arithmetic

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A linker for effective whole-program optimizations 7th

A linker for effective whole-program optimizations

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7th International Conference on High-Performance Computing and Networking, HPCN Europe 1999

作者： Cilio, Andrea G. M. Corporaal, Henk Delft University of Technology Computer Architecture and Digital Techniques Dept. Mekelweg 4 Delft2628CD Netherlands

ISBN: (纸本)3540658211

The use of a standard binary format in the later part of code generation promotes efficiency and interchangeability of tools, but leaves little information on the source file in the machine code representation. We propose a new approach to code generation, based on a single, highly structured internal format used during proper compilation, machine code generation and linkage. This format offers new opportunities for whole-program optimizations. We have implemented and tested a code generator based on this format. Although the use of traditional a binary format is more efficient, we believe that the increase in code size and compilation times are largely compensated by the opportunities offered by this new trajectory. To support this assertion, we discuss some of its potential applications. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Codes (symbols)

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G-Prop-II: Global optimization of multilayer perceptrons using GAs

G-Prop-II: Global optimization of multilayer perceptrons usi...

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1999 Congress on Evolutionary Computation, CEC 1999

作者： Castillo, P.A. Rivas, V. Merelo, J.J. Gonzalez, J. Prieto, A. Romero, G. Computer Science Dept. Avda. Madrid 35 E. 2307 1 Jaen Spain Dept. of Architecture and Computer Technology Campus de Fuentenueva s/n E. 1 807 1 Granada Spain

ISBN: (纸本)0780355369

A general problem in model selection is to obtain the right parameters that make a model fit observed data. For a multilayer perceptron (MLP) trained with backpropagation (BP), this means finding the right hidden layer size, appropriate initial weights and learning parameters. The paper proposes a method (G-Prop-II) that attempts to solve that problem by combining a genetic algorithm (GA) and BP to train MLPs with a single hidden layer. The GA selects the initial weights and the learning rate of the network, and changes the number of neurons in the hidden layer through the application of specific genetic operators. G-Prop-II combines the advantages of the global search performed by the GA over the MLP parameter space and the local search of the BP algorithm. The application of the G-Prop-II algorithm to several real world and benchmark problems shows that MLPs evolved using G-Prop-II are smaller and achieve a higher level of generalization than other perceptron training algorithms, such as QuickPropagation or RPROP, and other evolutive algorithms, such as G-LVQ. It also shows some improvement over previous versions of the algorithm. © 1999 IEEE.

关键词： Genetic algorithms

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Performance evaluation of the multimedia router with MPEG-2 video traffic 3rd

Performance evaluation of the multimedia router with MPEG-2 ...

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3rd International Workshop on Communication, architecture and Applications for Network-based Parallel Computing , CANPC 1999

作者： Caminero, Blanca Quiles, Francisco J. Duato, José Love, Damon S. Yalamanchili, Sudhakar Dept. of Computer Science Escuela Politécnica Superior de Albacete Universidad de Castilla La ManchaAlbacete02071 Spain Dept. of Information Systems and Computer Architecture Universidad Politécnica de Valencia P.O.B. 22012 Valencia46071 Spain School of Electrical and Computer Engineering Georgia Institute of Technology AtlantaGA30332-0250 Georgia

ISBN: (纸本)3540659153

The Multimedia Router (MMR) architecture is aimed at providing QoS to multimedia traffic in a local area environment, while retaining a compact and simple design. In this paper, we show some preliminary performance evaluation results. The workload was composed of a mix of synthetic CBR traffic and semi-synthetic VBR traffic. The latter was obtained from real MPEG-2 video sequences. We show that, with a simple scheduling algorithm, amenable for single-chip implementation, the link bandwidth utilization is quite satisfactory, while still providing acceptable delays to both CBR and VBR traffic. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Scheduling algorithms

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Real-time signal processing in a collision avoidance radar system using parallel computing 7th

Real-time signal processing in a collision avoidance radar s...

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7th International Conference on High-Performance Computing and Networking, HPCN Europe 1999

作者： Reijns, G.L. Van Gemund, A.J.C. Schier, J. Dept. of Information Technology and Systems Lab. of Computer Architecture and Digital Technique Delft University of Technology Netherlands Inst. of Information Theory and Automation Czech Academy of Sciences Czechia Int. Research Inst. for Telecom-transmission and Radar Delft University of Technology Netherlands

ISBN: (纸本)3540658211

COLARADO (an acronym for collision avoidance radar able to distinguish obstacles) is a system for use in the control of autonomously driven vehicles, having static radar antennas. By combining the echos, resulting from 2 continuously emitting transmitters and 3 receivers, it is possible to compute the locations of obstacles in 3 dimensions. The main problem is to separate the real obstacles from ghosts amongst noise and clutter, up to a distance of 12.8 m. This paper discusses the signal processing algorithms as well as the related real-time parallel computer hardware and system software. © Springer-Verlag Berlin Heidelberg 1999.

关键词： computer hardware

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Industrial evaluation of DRAM tests

Industrial evaluation of DRAM tests

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： A.J. van de Goer J. de Neef Dept. of Electr. Eng. Delft Univ. of Technol. Netherlands Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technnology Delft Netherlands

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.

关键词： Random access memory Testing Stress Leakage current Indium phosphide Information technology computer architecture Postal services Hip Electronic switching systems

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