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作者： Ellinghaus, P. Venter, P.J. Du Plessis, M. Rademeyer, P. Bogalecki, A.W. Ltd. Hatfield Pretoria 0083 South Africa Dept. of Electrical Electronic and Computer Engineering Carl and Emily Fuchs Institute for Microelectronics University of Pretoria Corner of University Road and Lynnwood Road Pretoria 0002 South Africa

The successful realization of optical interconnects for inter- and intra-chip communication strongly depends on the use of a light source that is compatible with existing, well established manufacturing processes - primarily CMOS/VLSI. The problematic integration of III-V light sources with CMOS technology has not been surmounted thus far. While silicon is ill-suited as an optical material, silicon based light sources present a huge advantage: complete monolithic integration using existing CMOS processes. This advantage can only be exploited if these devices show sufficient switching speed and optical power emission to make high speed clock and data transmission feasible. This paper illustrates the switching speed of silicon based light emitting devices in excess of 100 MHz and the viability of using such a device for an all-silicon optical link for clock and data distribution.

关键词： Silicon photonics

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Real-time constrained task scheduling in 3D chip multiprocessor to reduce peak temperature

Real-time constrained task scheduling in 3D chip multiproces...

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International Workshop on Wireless Network Algorithm and Theory

作者： Li, Jiayin Qiu, Meikang Niu, Jianwei Zhu, Yongxin Chen, Tianzhou Dept. of Electrical and Computer Engineering University of Kentucky Lexington KY 40506 United States State Key Lab. of Software Develop. Environment Beihang University Beijing 100191 China School of Microelectronics Shanghai Jiaotong University Shanghai 200240 China College of Computer Science Zhejiang University Hangzhou 310027 China

ISBN: (纸本)9780769543222

Chip multiprocessor technique has been implemented in embedded systems due to the tremendous computation requirements. Three dimension chip multiprocessor architecture has been studied recently for integrating more functionalities and providing higher performance. The high temperature on chip is a critical issue for the 3D architecture. In this paper, we propose an online thermal prediction model for 3D chip. Using this model, we present a task scheduling algorithm based on rotation scheduling to reduce the peak temperature on chip. We consider the data dependencies, especially the inter-iteration dependencies which are not well considered in most of the current thermal-aware task scheduling algorithms. Our simulation result shows that our algorithm can efficiently reduce the peak temperature up to 10 °C. © 2010 IEEE.

关键词： Embedded systems

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Rapid-Melting-Growth of Ge on Insulator using Cobalt (Co) Induced-Crystallized Ge as the Seed for Lateral Growth

Rapid-Melting-Growth of Ge on Insulator using Cobalt (Co) In...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Chunfu Zhang Thanh Hoa Phung Chunxiang Zhu Hong Joo Kang Meijun Chen Mingbin Yu Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Ins Institute of Microelectronics Singapore 117685

ISBN: (纸本)9781424457977

A new type of crystal seed, polycrystalline Ge (polyGe) formed by Co induced crystallization was used in the rapid-melting-growth (RMG) of Ge. With the polyGe seed, the grain size of Ge films obtained was significantly larger than the one using single crystal epitaxial Si as crystal seed and the one without any crystal seed. High quality (almost single crystal) Ge was obtained on 1 mm×1 mm square structure and single crystal Ge was obtained on 5 μm wide Ge wires by the RMG method with Co-induced poly-Ge as the crystal seed.

关键词： Silicon Wires Microwave integrated circuits Epitaxial growth Grain size Raman scattering

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Joint channel estimation and Markov Chain Monte Carlo detection for frequency-selective channels

Joint channel estimation and Markov Chain Monte Carlo detect...

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Sensor Array and Multichannel Signal Processing Workshop

作者： Hong Wan Rong-Rong Chen Jun Won Choi Andrew Singer James Preisig Behrouz Farhang-Boroujeny Département de Physique Théorique et appliquée Commissariat Energie Atomique Bruyeres-le-Cheitel France Dept. of Microelectronics Soochow University Suzhou China STMicroelectronics Crolles France Dept. of Electronic and Computer Engineering The Hong Kong University of Science and Technology Kowloon Hong Kong China

In this paper, we develop a novel approach for joint channel estimation and Markov Chain Monte Carlo (MCMC) detection for time-varying frequency-selective channels. First, we propose a sequential channel estimation (SCE) MCMC algorithm that combines an MCMC algorithm for data detection, and an adaptive least mean square (LMS) algorithm for channel tracking, in a sequential fashion. Then we develop a stochastic expectation maximization (SEM) MCMC algorithm that takes advantage of both the MCMC approach and the EM algorithm to find jointly important samples of the transmitted data and channel impulse response (CIR). The proposed algorithms provide a low-complexity means to approximate the optimal maximum a posterior (MAP) detection in a statistical fashion and are applicable to channels with long memory. Excellent behavior of the proposed algorithms is presented using both synthetic channels and real data collected from actual underwater acoustic experiments.

关键词： Channel estimation Detectors Least squares approximation Decoding Markov processes Joints Signal processing algorithms

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Low-power and high-SFDR direct digital frequency synthesizer based on hybrid CORDIC algorithm

Low-power and high-SFDR direct digital frequency synthesizer...

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2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

作者： Sung, Tze-Yun Ko, Lyu-Ting Hsin, Hsi-Chin Department of Microelectronics Engineering Chung Hua University Hsinchu City 30012 Taiwan Dept. of Computer Science and Information Engineering National United University Miaoli 36003 Taiwan

ISBN: (纸本)9781424438280

This paper describes the architecture and VLSI (very large scale integration) implementation of a direct digital frequency synthesizer (DDFS) based on a hybrid CORDIC (COordinate Rotation DIgital computer) algorithm. It is shown that the architecture can be implemented as a multiplier-less, small ROM ( 4x16 -bit) and pipelined data path. A SoC (system on chip) has been designed with 0/18m 1P6M CMOS, and emulated on Xilinx FPGA (field programmable gate array). The proposed technique uses hybrid CORDIC algorithm of sine and cosine functions to achieve more than 84.4-dBc spurious free dynamic range (SFDR). The performances of novel DDFS based on hybrid CORDIC algorithm compares favorably with digital circuit design, power consumption and SFDR. ©2009 IEEE.

关键词： System-on-chip

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Nanocrystalline silicon superlattice solar cells

Nanocrystalline silicon superlattice solar cells

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2009 MRS Spring Meeting

作者： Madhavan, Atul Chakravarty, Nayan Dalal, Vikram L. Dept. of Electrical and Computer Engineering Iowa State University United States Microelectronics Research Center Iowa State University Ames Iowa 50011 United States

ISBN: (纸本)9781605111261

We report on the growth and properties of nanocrystalline Si superlattice solar cells. The solar cells consisted of a stack of alternating layers of amorphous and nanocrystalline Si. The thickness of each of the two layers in the superlattice structure was varied independently. It was found that when the nanocrystalline layer thickness was low, increasing the thickness of the amorphous layer in the superlattice systematically reduced the 〈220〉 grain size, while the 〈111〉 grain size remained essentially invariant. This fact shows that by interposing an amorphous layer between two nanocrystalline layers forces the nano grains to renucleate and regrow. It was also found that when the amorphous Si layer was too thick, there were significant problems with hole transport through the device. Measurements of defect densities and effective diffusion lengths showed that there was an optimum thickness of the amorphous layer (about 10 nm) for which the defect density was the lowest and the diffusion length was the highest. We also show that the absorption coefficient in nano Si depends upon the grain size and can be increased significantly by increasing the grain size. © 2009 Materials Research Society.

关键词： Defect density

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Latency criticality aware on-chip communication

Latency criticality aware on-chip communication

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2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09

作者： Zheng, Li Jie, Wu Li, Shang Dick, Robert P. Yihe, Sun Tsinghua National Laboratory for Information Science and Technology Inst. of Microelectronics Tsinghua University Beijing 100084 China Dept. of Electrical and Computer Engineering University of Colorado Boulder CO 80309 United States Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9783981080155

Packet-switched interconnect fabric is a promising on-chip communication solution for many-core architectures. It offers high throughput and excellent scalability for on-chip data and protocol transactions. The main problem posed by this communication fabric is the potentially-high and nondeterministic network latency caused by router data buffering and resource arbitration. This paper describes a new method to minimize onchip network latency, which is motivated by the observation that only a small percentage of on-chip data and protocol traffic is latency-critical. Existing work focusing on minimizing average network latency is thus suboptimal. Such techniques expend most of the design, area, and power overhead accelerating latency-noncritical traffic for which there is no corresponding application-level speedup. We propose run-time techniques that identify latency-critical traffic by leveraging network data-transaction and protocol information. Latency-critical traffic is permitted to bypass router pipeline stages and latency-noncritical traffic. These techniques are evaluated via a router design that has been implemented using TSMC 65nm technology. Detailed network latency simulation and hardware characterization demonstrate that, for latencycritical traffic, the proposed solution closely approximates the ideal interconnect even under heavy load while preserving throughput for both latency-critical and noncritical traffic. © 2009 EDAA.

关键词： Routers

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Observation of combined self-heating and hot-carrier degradation in n-Type Poly-Si thin-film transistors

Observation of combined self-heating and hot-carrier degrada...

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2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009

作者： Zhang, Meng Wang, Mingxiang Wang, Huaisheng Zhang, Dongli Wong, Man Dept. of Microelectronics Soochow University Suzhou 215021 China Dept. of Electronic and Computer Engineering Hong Kong University of Science and Technology Kowloon Hong Kong Hong Kong Dept.of Electrical and Electronic Engineering Nanjing Institute of Railway Technology Suzhou 215137 China

ISBN: (纸本)9781424439102

Different degradation behaviors of n-type poly-Si thin film transistors under dynamic voltage stresses have been demonstrated. Combined self-heating (SH) and hot-carrier (HC) degradation is first observed under a certain dynamic stress, where the device degradation is dependent on the pulse rising time (tr ) but independent of the falling time (tf) Absence of the degradation during tf is attributed to the SH suppression of the HC mechanism. Typical HC degradation under pure Vg pulses is dependent on tf but in dependent of tf While in the channel saturation mode, AC HC effect is dependent on both t r, and tf For the low frequency synchronized stresses, AC SH degradation behavior related to the pulse duty time is the same as DC SH. ©2009 IEEE.

关键词： Hot carriers

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Nanocrystalline Silicon Superlattice Solar cells

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MRS Online Proceedings Library 2009年第1期1153卷 1-6页

作者： Atul Madhavan Nayan Chakravarty Vikram L. Dalal Dept. of Electrical and Computer Engineering Ames USA Microelectronics Research Center Iowa State University Ames USA

We report on the growth and properties of nanocrystalline Si superlattice solar cells. The solar cells consisted of a stack of alternating layers of amorphous and nanocrystalline Si. The thickness of each of the two layers in the superlattice structure was varied independently. It was found that when the nanocrystalline layer thickness was low, increasing the thickness of the amorphous layer in the superlattice systematically reduced the <220> grain size, while the <111> grain size remained essentially invariant. This fact shows that by interposing an amorphous layer between two nanocrystalline layers forces the nano grains to renucleate and regrow. It was also found that when the amorphous Si layer was too thick, there were significant problems with hole transport through the device. Measurements of defect densities and effective diffusion lengths showed that there was an optimum thickness of the amorphous layer (about 10 nm) for which the defect density was the lowest and the diffusion length was the highest. We also show that the absorption coefficient in nano Si depends upon the grain size and can be increased significantly by increasing the grain size.

关键词： nanoscale photovoltaic Si

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Sharp absorption and high temperature thermal emission from simple metallic photonic crystals

Sharp absorption and high temperature thermal emission from ...

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2009 MRS Spring Meeting

作者： Biswas, Rana Zhou, Dayu Puscasu, Irina Johnson, Edward Taylor, Andrew Zhao, Weijun Depts. of Physics and Astronomy Microelectronics Research Center Iowa State University Ames IA 50011 United States Dept. of Electrical and Computer Engineering Microelectronics Research Center Iowa State University Ames IA 50011 United States ICX Photonics Billerica MA 01821 United States

ISBN: (纸本)9781615677795

We design and fabricate metallic photonic crystals with sharp absorption peaks in the infrared regime. We have fabricated a metallic photonic crystal consisting of a triangular lattice of holes in a silicon layer conformally coated with gold at a lattice pitch of 3.8 microns. Conventional lithographic and deep reactive ion etching was used. The photonic crystal exhibits a deep reflection minimum and sharp thermal emission peak near the lattice spacing. Measurements agree well with rigorous scattering matrix simulations. This simple single-layer structure with a single patterned exposure has no emission sidebands and can be scaled to other lattice spacings. © 2009 Materials Research Society.

关键词： Photonic crystals

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