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3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005

作者： Achigui, Herve F. Fayomi, Christian J. B. Sawan, Mohamad Polystim Neurotechnologies Laboratory Electrical Engineering Dept. École Polytechnique de Montréal Microelectronics Laboratory Computer Science Dept. Université du Québec à Montréal

ISBN: (纸本)0780389344

In this paper, we describe a novel class AB opamp based on dynamic threshold voltage transistors (DTMOS) for low voltage (1-V), low power and low noise applications. The opamp is used to build the front-end receiver part of a near infrared spectroreflectometry (NIRS) device. The opamp has a two-stage configuration;DTMOS pseudo pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class AB output. Experimental measurements from previous designs confirm the usage of a DTMOS device to build a 1-V opamp, using standard 0.18-μm CMOS technology. The performed post-layout simulation results show an input referred noise of 107 nV/√Hz at 1 kHz, and a power consumption of 33.1 μW under 5 pF and 10 kΩ loads. The dc open loop gain is 60 dB, and a unity frequency of 2.73 MHz. The opamp has a CMRR of 100 dB, and input and output swings of 0.6 V and 0.8 V respectively. © 2005 IEEE.

关键词： Operational amplifiers

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A performance and power co-optimization approach for modern processors

A performance and power co-optimization approach for modern ...

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Fifth International Conference on computer and Information Technology, CIT 2005

作者： Zhu, Yongxin Wong, Weng-Fai Koh, Cheng-Kok Dept. of Computer Science National University of Singapore Singapore 117543 Singapore School of Microelectronics Shanghai Jiao Tong University Shanghai 200030 China Dept. of Electrical and Computer Engineering Purdue University West Lafayette IN 47907-2035 United States

In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually required to verify whether a design meets both performance and power requirements. In this paper, an analytical co-optimization approach based on an integrated workload, performance and power model for modem processors is described and studied. A design space consisting of more than 15 architectural and workload parameters can be quickly explored for co-optimization. Validation with measured results obtained from simulators as well as physical processors showed that the model has a good degree of accuracy. We shall describe the details of approach and the model, and show how to apply the approach to the problem of co-optimizing the power and performance of processor design. With the completeness, flexibility and efficiency, our approach provides clear insights into the tradeoffs of designs for performance and power. © 2005 IEEE.

关键词： Program processors

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A 1 V low power, low noise DTMOS based NIRS front-end receiver

A 1 V low power, low noise DTMOS based NIRS front-end receiv...

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9th World Multi-Conference on Systemics, Cybernetics and Informatics, WMSCI 2005

作者： Achigui, Herve F. Sawan, Mohamad Fayomi, Christian J.B. PolySTIM Neurotechnology Laboratory Electrical Engineering Dept. École Polytechnique de Montréal Canada Microelectronics Laboratory Computer Science Dept. Université du Québec à Montréal Canada

ISBN: (纸本)9806560582

We have developed a novel analog front-end part of a wireless brain oxymeter receiver instrument based on nearinfrared spectroreflectometry (NIRS). The NIRS receiver makes use of dynamic threshold transistors (DTMOS) for low voltage (1-V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs are in a class AB configuration, and uses DTMOS devices for input common-mode range enhancement. Post-layout simulations under a 5 pF load, using 0.18 μm CMOS technology results are, for the OTA, an input referred noise of 134 nV/√Hz at 1 kHz, and a power consumption of 16.7 μW without any extra noise reduction technique. Also, the TIA gives 208 pA/√Hz at 1 kHz, while having a power consumption of only 10.9 μW. The proposed analog front-end circuits have been used to implement a NIRS receiver instrument with improved ultra low-light level measurements, high resolution and good temperature stability.

关键词： Operational amplifiers

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Source/drain germanium condensation for P-channel strained ultra-thin body transistors

Source/drain germanium condensation for P-channel strained u...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Chui, King-Jien Ang, Kah-Wee Madan, Anuj Wang, Huiqi Tung, Chih-Hang Wong, Lai-Yin Wang, Yihua Choy, Siew-Fong Balasubramanian, N. Li, Ming Fu Samudra, Ganesh Yeo, Yee-Chia Silicon Nano Device Lab. Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore Institute of Microelectronics 11 Science Park Road Singapore 117685 Singapore

ISBN: (纸本)078039268X

This paper reports a novel technique to fabricate uniaxial compressive strained P-channel transistors with Silicon-Germanium (SiGe) source and drain (S/D) Stressors. The process involves local Ge condensation of a selectively grown SiGe region, thus driving Ge into and enriching the Ge concentration in the source and drain regions adjacent to the transistor channel. The process is particularly suitable for ultra-thin-body (UTB) transistors since it eliminates the need for a Si recess etch prior to SiGe epitaxy. In addition, the required thermal budget for Ge condensation is not prohibitive for UTB structures. High Ge mole fraction could be achieved in the S/D regions, leading to higher strain levels in the transistor channel. We demonstrate the feasibility of this technique in Silicon-on-Insulator (SOI) P-MOSFETs with a gate length L G of 90 nm. Drive current IDsat enhancement of up to 35% was observed. © 2005 IEEE.

关键词： Transistors

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A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor

A novel CMOS compatible L-shaped impact-ionization MOS (LI-M...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Toh, Eng-Huat Wang, Grace Huiqi Lo, Guo-Qiang Balasubramanian, Narayanan Tung, Chih-Hang Benistant, Francis Chan, Lap Samudra, Ganesh Yeo, Yee-Chia Silicon Nano Device Lab. Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore Institutue of Microelectronics 11 Science Park Road Singapore 117685 Singapore

ISBN: (纸本)078039268X

This paper reports a novel L-shaped Impact-ionization MOS (LI-MOS) transistor technology that achieves subthreshold swing well below 60 mV/decade at room temperature. First, the LI-MOS transistor is CMOS process compatible, and requires little process modification for integration in a manufacturable process. Second, the LI-MOS structure employs raised source/drain (S/D) regions that enable controllability and scalability of the impact ionization region (I-region). Third, the LI-MOS has superior compactness over previously reported I-MOS device structures. Fourth, the LI-MOS enables the integration of novel materials for band gap and strain engineering to enhance the impact ionization rate in the I-region. Based on the above technology, we demonstrate a record subthreshold swing of 4.5 mV/decade at room temperature for a 100 nm gate length device that incorporates a SiGe I-region. The smallest impact-ionization-based MOS device with a gate length of 60 nm is also demonstrated with a subthreshold swing that is well below 60 mV/decade. © 2005 IEEE.

关键词： MOS devices

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Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement

Thin body silicon-on-insulator N-MOSFET with silicon-carbon ...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Ang, Kah-Wee Chui, King-Jien Bliznetsov, Vladimir Wang, Yihua Wong, Lai-Yin Tung, Chih-Hang Balasubramanian, N. Li, Ming-Fu Samudra, Ganesh Yeo, Yee-Chia Silicon Nano Device Lab. Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore Institute of Microelectronics 11 Science Park Road Singapore 117685 Singapore

ISBN: (纸本)078039268X

We report a novel strained n-channel transistor structure featuring silicon-carbon (SiC) source and drain (S/D) regions formed on thin body SOI substrate. The SiC material is pseudomorphically grown by selective epitaxy and the carbon mole fraction incorporated is 1%. Lattice mismatch between SiC and Si results in uniaxial tensile strain in the Si channel region which contributes favorably to electron mobility enhancement. Drive current IDsat enhancement of 25% was observed for 90 nm gate length LG transistors, and IDsat enhancement of up to 35% was observed at LG of 70 nm. In addition, drive current enhancement shows dependence on device width and channel orientation. All transistors were formed on (001) SOI substrates. The largest IDsat enhancement is observed for transistors with the [010] channel orientation. © 2005 IEEE.

关键词： MOSFET devices

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Study of Germanium Diffusion in HfO 2 Gate Dielectric of MOS Device Application

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MRS Online Proceedings Library 2005年第1期829卷 432-437页

作者： Qingchun Zhang Nan Wu L. K. Bera Chunxiang Zhu Silicon Nano Device Lab Dept of Electrical and Computer Engineering National University of Singapore Singapore Institute of Microelectronics Singapore

Significant germanium incorporation into HfO2 gate dielectrics has been found after thermal annealing in germanium MOS device. The dependences of germanium incorporation in HfO2with dielectric deposition method, annealing temperature and annealing ambient were extensively studied by means of physical analytical methods such as SIMS and XPS. MOCVD (metal organic chemical vapor deposition) technique shows stronger germanium incorporation than PVD (physics vapor deposition) while surface nitridation of germanium can effectively suppress the Ge-incorporation. In addition, the results indicate that a thermal budget higher than 500oC in device fabrication results in apparent Ge out-diffusion. And the germanium out-diffusion is found to be enhanced under oxygen environment.

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Vertical-structured Ni/n-GaN schottky diode with electroplating nickel substrate

Vertical-structured Ni/n-GaN schottky diode with electroplat...

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63rd Device Research Conference, DRC'05

作者： Wang, Shui-Jinn Chang, Shu-Cheng Uang, Kai-Ming Liou, Bor-Wen Institute of Microelectronics Department of Electrical Engineering National Cheng Kung University Tainan 701 Taiwan Department of Electronic Engineering Wu-Feng Institute of Technology Chiayi Taiwan Dept. of Computer Science and Information Eng. Wu-Feng Institute of Technology Chia-yi Taiwan

ISBN: (纸本)0780390407

For the past decade, most of vertical device applications of GaN were processed by either wafer bonding or direct epitaxy on SiC or GaN wafer. However, the former usually suffers from large strain between GaN and bonding wafer because the high temperature and high pressure bonding process, and the later is not cost effective because of using SiC or GaN substrate. In this work, a novel vertical structure of Ni/n-GaN Schottky barrier diode (SBD) with metallic substrate employing nickel electroplating and laser lift-off (LLO) processes is proposed and its electrical characteristics is reported. Figure 1 shows the processes flow of device fabrication. The GaN epi-layer consists of a 25-nm-thick GaN buffer layer, a 2-μm-thick undoped GaN and a 1.5-μm-thick GaN films with doping concentration of around 5×1018 cm -3, which were grown subsequently on (0001) sapphire substrates by metal organic chemical vapor deposition. The Ti(15 nm)/Al(600 nm)/Ti(15 nm)/Au(100 nm) metal system were used as the ohmic contact which were deposited in sequence on n+ GaN using e-beam evaporator under a background pressure of around 1×10-6 torr. After that, the samples were subjected to rapid thermal annealing at 800°C in Ar for 30 sec to further improve the ohmic behavior. Note that the ohmic metal not only ensures good contact properties to both n+ GaN layer and the upper nickel layer, but also provids a good current conductive path for nickel electroplating. The electroplating process was conducted under a current of around 1.7 A for 30 min with the plating solution kept at around 55°C and a nickel layer with a thickness of around 50 μm was achieved. To remove the sapphire substrate, a 248 nm KrF Excimer laser with 800 mJ/cm2 laser power was used to cause local heating at the GaN/sapphire interface which in turn lead to the decomposition of the GaN. After the LLO process, the sample was then heated to 40°C and the electroplated-Ni adhered GaN epilayer was then separated from the sapphire subs

关键词： Schottky barrier diodes

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General chairs’ message

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2005年 3326 LNCS卷 V-VI页

作者： Das, Nabanita Sinha, Bhabani P. Sen, Arunabha Das, Sajal K. Indian Statistical Institute Advanced Computing and Microelectronics Unit 203 B.T. Road Kolkata700 108 India Arizona State University Dept. of Computer Science and Engineering TempeAZ United States University of Texas at Arlington Dept. of Computer Science and Engineering ArlingtonTX76019-0015 United States

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Block SAPOR: block second-order Arnoldi method for passive order reduction of multi-input multi-output RCS interconnect circuits 05

Block SAPOR: block second-order Arnoldi method for passive o...

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Asia and South Pacific Design Automation Conference

作者： Bang Liu Xuan Zeng Yangfeng Su Jun Tao Zhaojun Bai C. Chiang Dian Zhou Microelectronics Dept Fudan University Shanghai P.R. China Mathematics Dept. Fudan University Shanghai P.R. China Department of Computer Science University of California Davis Davis CA USA Advanced Technology Group Synopsys Inc Mountain View CA USA Electrical Engineering Dept. University of Texas at Dallas Richardson TX USA

ISBN: (纸本)9780780387379

Recently model order reduction techniques for second-order systems have obtained many research interests for the simulation of RCS interconnect circuits employing susceptance elements. In this paper, we propose a Block SAPOR (Block Second-order Arnoldi method for Passive Order Reduction) for multi-input multi-output RCS circuits. The proposed Block SAPOR algorithm can simultaneously guarantee passivity and achieve higher accuracy than the first order reduction technique PRIMA. Most importantly, the reduced system matrices obtained by the proposed method can preserve the structure of the original system matrices. Such a nice property makes it possible to construct an equivalent RCS circuit for the reduced system.

关键词： Integrated circuit interconnections RLC circuits Circuit simulation Inductance Reduced order systems Application specific integrated circuits microelectronics Mathematics computer science Mathematical model

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