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10th International European Conference on Parallel Processing, Euro-Par 2004

作者： Kuzmanov, Georgi Gaydadjiev, Georgi Vassiliadis, Stamatis Computer Engineering Lab Microelectronics and Computer Engineering Dept EEMCS TU Delft Mekelweg 4 CD Delft2628 Netherlands

ISBN: (纸本)3540229248

We focus on the parallel access of randomly aligned rectangular blocks of visual data. As an alternative of traditional linearly addressable memories, we suggest a memory organization based on an array of memory modules. A highly scalable data alignment scheme incorporating module assignment functions and a new generic addressing function are proposed. To enable short critical paths and to save hardware resources, the addressing function implicitly embeds the module assignment functions and it is separable. A corresponding design is evaluated and compared to existing schemes and is found to be cost-effective. © Springer-Verlag Berlin Heidelberg 2004.

关键词： Cost effectiveness

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ASIC design of a kohonen neural network microchip

ASIC design of a kohonen neural network microchip

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2004 IEEE International Conference on Semiconductor Electronics, ICSE 2004

作者： Rajah, Avinash Hani, Mohamed Khalil Dept. of Microelectronics and Computer Engineering Faculty of Electrical Engineering Universiti Teknologi Malaysia 81300 Skudai Johor Bahru Malaysia

ISBN: (纸本)0780386582

This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um C05M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology. © 2004 IEEE.

关键词： Application specific integrated circuits

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Impact of metal gate work function on nano CMOS device performance

Impact of metal gate work function on nano CMOS device perfo...

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Hou, Y.T. Low, Tony Xu, Bin Li, Ming-Fu Samudra, G. Kwong, D.L. SNDL Dept. Electrical and Computer Engineering National University of Singapore 119260 Singapore Institute of Microelectronics 117685 Singapore Dept. Electrical and Computer Engineering University of Texas Austin TX 78712 United States

We studied two effects in the metal gate work function engineering in nano CMOSFETs: (1) Gate work function shifts induced by carrier quantization in Si and Ge ultra-thin body FETs with sub-10 nm body thickness and different surface orientations. Guidelines for metal gate work function engineering are provided and technical challenges identified;(2) We presented a systematic study on gate tunneling characteristics of metal gate CMOSFETs. A reduction of gate to source/drain extension tunneling is found when using near mid-gap metal gate in SOI CMOS, especially when using high-K dielectric. Benefits of this reduction to transistor off-state leakage and to future CMOS scaling were analyzed. © 2004 IEEE.

关键词： CMOS integrated circuits

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Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon ...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Ang, Kah Wee Chui, King Jien Bliznetsov, Vladimir Du, Anyan Balasubramanian, N. Li, Ming Fu Samudra, Ganesh Yeo, Yee-Chia Silicon Nano Device Lab Dept. of Electrical and Computer Engineering National University of Singapore Singapore 117576 Institutue of Microelectronics 11 Science Park Road Singapore 117685

This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The strained N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of SiC in the S/D regions. The carbon mole fraction incorporated is 1.3%. Lattice mismatch of ∼0.6S% between SiC and Si results in horizontal tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The conduction band offset ΔEc between the SiC source and the strained-Si channel also contributes to increased electron injection velocity from the source. Implementation of the SiC Stressors provides significant drive current I DS enhancement in the N-MOSFETs. IDS enhancement of 50% was observed for a gate length of 50 nm. © 2004 IEEE.

关键词： MOSFET devices

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A comparison study of high-density MIM capacitors with ALD HfO 2-Al2O3 laminated, sandwiched and stacked dielectrics

A comparison study of high-density MIM capacitors with ALD H...

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Ding, Shi-Jin Hu, H. Zhu, Chunxiang Kim, S.J. Li, M.F. Cho, B.J. Chin, A. Kwong, D.-L. SNDL Dept. of Electrical and Computer Eng National University of Singapore Singapore 119260 Singapore Institute of Microelectronics Singapore 117685 Singapore Dept. of Electronics Engineering National Chiao Tung Univ. Taiwan Dept. of Electrical and Computer Engineering University of Texas Austin TX 78712 United States

The HfO2-Al2O3 laminate MIM capacitor exhibits superior performances to the stack and sandwich counterparts, including the smallest linear voltage coefficient of capacitance (β) and leakage current, the highest breakdown voltage, the longest time-to-breakdown as well as the most stable quadratic voltage coefficient of capacitance (a) and capacitance under CVS due to weak electron trapping. The underlying mechanism is likely attributed to the alternate insertions of Al2O3 into the bulk HfO2, thereby preventing crystallization of HfO 2 film. © 2004 IEEE.

关键词： MIM devices

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Schottky s/d MOSFETs with high-Kgate dielectrics and metal gate electrodes

Schottky s/d MOSFETs with high-Kgate dielectrics and metal g...

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Zhu, Shiyang Chen, Jingde Yu, H.Y. Whang, S.J. Chen, J.H. Shen, C. Li, M.F. Lee, S.J. Zhu, Chunxiang Chan, D.S.H. Du, Anyan Tung, C.H. Singh, Jagar Chin, Albert Kwong, D.L. Silicon Nano Device Lab. Dept. of ECE National University of Singapore Singapore 119260 Institute of Microelectronics Singapore 117685 Dept. of Microelectronics Fudan University Shanghai 200433 China Dept. of Electronics Engineering National Chiao Tung University Hsinchu 300 Taiwan Dept. Electrical and Computer Eng. Univ. of Texas Austin TX 78712 United States

Bulk Schottky suicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0-2.5nm HfO2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi suicide show excellent electrical performance of Ion ∼10 7-108 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi2-x silicide have also demonstrated a very promising characteristic with a recorded high Ion/Ioff radio of∼ 107 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, -showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology. © 2004 IEEE.

关键词： Electrodes

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Single-crystalline silicon thin-film transistor on glass

Single-crystalline silicon thin-film transistor on glass

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2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT 2004

作者： Shi, Xuejie Wong, Man Henttinen, K. Suni, T. Suni, I. Lau, S.S. Dept. of Electrical and Electronic Engineering Hong Kong University of Science and Technology Clear Water Bay Kowloon Hong Kong VTT Center for Microelectronics Tietotie 3 Espoo Finland Dept. of Electrical and Computer Engineering University of California San Diego San Diego CA 92093-0407 United States

Single-crystalline silicon-on-glass (cSOG) has been obtained using an "ion-cutting" based layer-transfer technique. Compared to previous attempts of realizing cSOG, extended silicon etching is not required and bulk silicon, instead of the relatively more expensive silicon-on-insulator donor wafers, can be used. Thin-film transistors based on cSOG have been fabricated and characterized. The stability of cSOG Thin-film transistors with or without laser-induced annealing is reported. ©2004 IEEE.

关键词： Thin film transistors

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Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon ...

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International Electron Devices Meeting (IEDM)

作者： Kah Wee Ang King Jien Chui V. Bliznetsov Anyan Du N. Balasubramanian Ming Fu Li Ganesh Samudra Yee-Chia Yeo Silicon Nano Device Laboratory Department of Electrical and Computer Engineering National University of Singapore Singapore Dept of Electrical and Computer Engineering Institutue of Microelectronics 11 Science Park Road Singapore 117685 Singapore Dept of Electrical and Computer Engineering Institutue of Microelectronics 11 Science Park Road Singapore 117685 Singapore Singapore

This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The strained N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of SiC in the S/D regions. The carbon mole fraction incorporated is 1.3%. Lattice mismatch of /spl sim/0.65% between SiC and Si results in horizontal tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The conduction band offset /spl Delta/E/sub c/ between the SiC source and the strained-Si channel also contributes to increased electron injection velocity from the source. Implementation of the SiC stressors provides significant drive current I/sub DS/ enhancement in the N-MOSFETs. I/sub DS/ enhancement of 50% was observed for a gate length of 50 nm.

关键词： MOSFET circuits Silicon carbide Tensile strain Electron mobility Intrusion detection Epitaxial growth Heterojunctions Implants Sputter etching microelectronics

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Analysis of the Three-Dimensional Nanoscale Relationship of Ge Quantum Dots in a Si Matrix Using Focused Ion Beam Tomography

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MRS Online Proceedings Library 2004年第1期818卷 181-187页

作者： Alan J. Kubis Thomas E. Vandervelde John C. Bean Derren N. Dunn Robert Hull Dept of Materials Science and Engineering Univ. of Virginia Charlottesville U.S.A. Dept of Physics Univ. of Virginia Charlottesville U.S.A. Dept of Electrical and Computer Engineering Univ. of Virginia Charlottesville U.S.A. IBM Microelectronics Hopewell Junction U.S.A.

It is well documented that buried layers in quantum dot (QD) superlattices influence the position of quantum dots in the subsequently grown layers through strain field interactions (e.g.1,23,4). Using the Focused Ion Beam (FIB) tomographic technique we have reconstructed the 3D relationship of successive layers of coherent Ge QDs separated by epitaxial Si capping layers - a “QD superlattice”. Techniques such as Atomic Force Microscopy (AFM) and Scanning Tunneling Microscopy (STM) can only look at a single surface layer of QDs or, in the case of Transmission Electron Microscopy (TEM), look at a two-dimensional projection of a three-dimensional volume so that 3D relationships need to be inferred. Since the strain interactions are complex, an enhanced fundamental understanding of these self-organization mechanisms can more directly be obtained from full 3D reconstructions of these structures. By capping with Si at 300oC we were able to grow QD superlattices with QDs tens of nanometers in height. This places them within the resolution of the FIB tomographic technique to reconstruct. Using the FIB we performed in-situ serial sectioning of the QD superlattice and then reconstructed the QD superlattice. The reconstruction was then analyzed to investigate the ordering of the QDs. Results from a reconstruction of a superlattice matrix will be presented with analysis of the self-ordering of the QDs. Observations of a novel self-limiting (in height) morphology, the quantum mesa, associated with the capping technique used will also be discussed.

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Schottky s/d MOSFETs with high-K gate dielectrics and metal gate electrodes

Schottky s/d MOSFETs with high-K gate dielectrics and metal ...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Shiyang Zhu Jingde Chen H.Y. Yu S.J. Whang J.H. Chen C. Shen M.F. Li S.J. Lee Chunxiang Zhu D.S.H. Chan Anyan Du C.H. Tung J. Singh A. Chin D.L. Kwong Dept. of Microelectronics Fudan University Shanghai China Silicon Nano Device Lab National University of Singapore Singapore Institute of Microelectronics Singapore Chinese Academy and Sciences Singapore Dept. of Electronics Engineering National Chiao Tung University Hsinchu China Department of Electrical & Computer Engineering University of Technology Austin TX USA Dept. Electrical & Computer Eng. Univ of Texas Austin TX USA

Bulk Schottky silicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0 /spl sim/ 2.5nm HfO/sub 2/ gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi silicide show excellent electrical performance of I/sub on//I/sub off//spl sim/ 10/sup 7/ - 10/sup 8/ and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi/sub 2-x/ silicide have also demonstrated a very promising characteristic with a recorded high I/sub on//I/sub off/ radio of /spl sim/ 10/sup 7/ and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.

关键词： MOSFETs Electrodes Silicides Temperature CMOS technology Hafnium oxide Implants High-K gate dielectrics High K dielectric materials Inorganic materials

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