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13th International Symposium on Integrated Ferroelectrics

作者： Yi, Insook Kim, Daeik Kim, Sukpil Lee, Yongkyun Kim, Changjung Chung, Ilsub Microelectronics and Device Laboratory Samsung Advanced Institute of Technology P.O.Boxll1 Suwon 440-600 Korea Republic of School of Electrical and Computer Engineering Sungkyunkwan University 300 Chunchun-Dong Jangan-Ku Suwon 440-746 Dept. Materials Science and Engineering Korea Advanced Institute of Science and Technology 373- 1 Kusung-Dong Yusung-Ku Daejeon

Improvement of reliability, specially high endurance and retention characteristics, of PZT capacitors has been a main question for high density FeRAM development. Pt/IrO2 hybrid electrode has been suffered from the hydrogen degradation due to the strong catalytic function of Pt. Thus, IrO2 electrode can be a good candidate for the minimizing hydrogen related degradation. We have investigated the variation in ferroelectric properties such as fatigue, retention and hydrogen effect of PZT capacitors grown on the IrO2 electrodes in comparison with those grown on the Pt/IrO2 hybrid electroe. © 2001 Taylor and Francis.

关键词： Capacitors

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Special purpose image convolution with evolvable hardware

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EvoWorkshops 2000: 2nd European Workshop on Evolutionary Computation in Image Analysis and Signal Processing, EvoIASP 2000, 1st European Workshop on Evolutionary Computation in Systems, Control and Drives in Industry, Evo-SCONDI 2000, 2nd European Workshop on Evolutionary Telecommunications, EvoTel 2000, 1st European Workshop on Evolutionary Scheduling and Timetabling, EvoStim 2000, 3rd European Workshop on Evolutionary Robotics, EvoRob 2000 and 1st European Workshop on Evolutionary Aeronautics, EvoFlight 2000 held in conjunction with European Conference on Genetic Programming, EuroGP 2000 and 3rd International Conference on Evolvable Systems, ICES 2000

作者： Dumoulin, Joe Foster, James A. Frenzel, James F. McGrew, Steve New Light Industries Ltd SpokaneWA United States Center for Secure and Dependable Software U. Idaho MoscowID United States Microelectronics Research and Communications Inst U. Idaho MoscowID United States Dept. of Computer Science U. Idaho MoscowID United States Dept. of Electrical and Computer Engineering U. Idaho MoscowID United States

ISBN: (纸本)3540673539

In this paper, we investigate a unique method of inventing linear edge enhancement operators using evolution and reconfigurable hardware. We show that the technique is motivated by the desire for a totally automated object recognition system. We show that an important step in automating object recognition is to provide flexible means to smooth images, making features more obvious and reducing interference. Next we demonstrate a technique for building an edge enhancement operator using evolutionary methods, implementing and testing each generation using the Xilinx 6200 family FPGA. Finally, we present the results and conclude by mentioning some areas of further investigation. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Object recognition

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Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Low power/low voltage high speed CMOS differential track and...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

关键词： Low voltage Latches Delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process

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Photonic crystal defect microcavities with indium arsenide quantum dots

Photonic crystal defect microcavities with indium arsenide q...

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IEEE Photonics Conference (IPC)

作者： T. Yoshie O. Painter A. Scherer D. Huffaker D. Deppe Dept. of Electr. Eng. California Inst. of Technol. Pasadena CA USA Department of Electrical Engineering California Institute of Technology Pasadena CA USA Microelectronics research Center Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

The coupling of InAs QDs emission to the two dimensional photonic crystal defect cavity has been demonstrated for the first time and a narrow filtered emission linewidth could be observed. We describe the emission from 2D photonic crystals that contain an InAs QDs active layer. The epitaxial layers were grown on [001] GaAs by molecular beam epitaxy.

关键词： Photonic crystals Microcavities Indium Quantum dots US Department of Transportation Optical pumping Resonance Anisotropic magnetoresistance Etching Superlattices

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An SOI single-electron transistor 25

An SOI single-electron transistor

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25th Annual IEEE International Silicon-on-Insulator Conference, SOI 19999

作者： Tang, Xiaohui Baie, X. Bayot, V. Van De Wiele, F. Colinge, J.P. Microelectronics Lab Universite Catholique de Louvain Louvain-la-Neuve1348 Belgium Dept. Electrical and Computer Engineering University of California DavisCA95616 United States

ISBN: (纸本)0780354567

Single-electron transistors (SETS) are currently being investigated by many research groups as possible devices for ultra-high-density, low-power information processing or storage systems. A single-electron transistor consists of two tunnel junctions (TJ) connected to the source and the drain, a center floating node and a capacitance connected to the device gate (Figure 1). It takes a finite minimum source-to center node bias to inject an electron into the node by tunneling. This effect is called "Coulomb blockade". This bias depends on the gate voltage which influences the node voltage. When an electron is injected from the source into the center node through a tunnel junction the node voltage suddenly drops by a value q/C, where q is the electron charge and C is the total node capacitance. Because of the Coulomb blockade effect the source bias needs to be substantially decreased to inject another electron into the node. But the electron can easily escape into the drain through the tunnel effect, and another electron can be injected by the source into the node and current flow is observed. As a result of the Coulomb blockade, there are diamond-shaped zones in the VG-VD plane where no current flow is possible.' © 1999 IEEE.

关键词： Single electron transistors

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Multi-terminal net routing for partial crossbar-based multi-FPGA systems 99

Multi-terminal net routing for partial crossbar-based multi-...

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Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

作者： Abdel Ejnioui N. Ranganathan Center for Microelectronics Research University of South Florida Tampa FL Dept. of Electrical & Computer Engineering The University of Texas at El Paso El Paso Texas

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Realization of self-repairing and evolvable hardware structures by means of implicit self-configuration 1

Realization of self-repairing and evolvable hardware structu...

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1st NASA/DoD Workshop on Evolvable Hardware, EH 1999

作者： Moreno, J.M. Madrenas, J. Cabestany, J. Canto, E. Kielbik, R. Faura, J. Insenser, J.M. Technical University of Catalunya Dept. of Electronic Engineering Building C4 Campus Nord c/Gran Capita s/n Barcelona08034 Spain Technical University of Lodz Dept. of Microelectronics and Computer Science al. Politechniki Lodz53-590 Poland SIDSA PTM Torres Quevedo 1 Tres Cantos28760 Spain

ISBN: (纸本)0769502563

In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design. © 1999 IEEE.

关键词： Dynamic models

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Rate control for a video coder using learning automata

Rate control for a video coder using learning automata

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IEEE International Conference on Systems, Man and Cybernetics

作者： R. Chandramouli S. Kumar N. Ranganathan Dept. of Comput. Sci. & Eng. Univ. of South Florida Tampa FL USA Center for Microelectronics Research Department of Computer Science and Engineering University of South Florida Tampa USA

In this paper, a rate controller for a H.261 based video encoder is proposed. The rate controller adaptively chooses the optimal channel matched quantizer using a stochastic learning automaton. The automaton learns the channel characteristics based on a one bit feedback from the decoder. The rate control algorithm is shown to converge to the optimal choice of the quantizer very quickly for various channel bit error probabilities and for different video sequences. The adaptation can be achieved in real-time. The peak signal to noise ratio of the received video signal is seen to be better using the proposed approach.

关键词： Automatic control Learning automata PSNR Video compression Decoding Error probability Videoconference Forward error correction Quantization Stochastic processes

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OPTIMAL SYSTOLIC ARRAYS FOR REAL-TIME IMPLEMENTATION OF THE MODIFIED COVARIANCE SPECTRAL ESTIMATOR

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Parallel Algorithms and Applications 1997年第1-2期11卷 71-96页

作者： Stephen J. Bellis[a] Peter J. Fish[a] William P. Marnane[b] [a] School of Electronic Engineering and Computer Systems University of Wales Bangor UK [b] Dept of Electrical Engineering and Microelectronics University College Cork Ireland

The Modified Covariance method of spectral estimation, proposed as a replacement of the conventional short term Fourier transform for use with pulsed Doppler ultrasound blood flow detectors in order to improve time/frequency resolution, is computationally far more demanding. The use of an application specific architecture for real-time implementation is of interest. A cost/benefit selection of systolic arrays, firstly for a matrix solution method with suitable bus width and secondly for calculation of covariance matrix elements, led to the choice of Cholesky matrix decomposition, 12 bit bus width and a bi-linear systolic array designed using a data dependence graph method.

关键词： Spectral estimation Doppler ultrasound Modified Covariance method systolic array ALPHA data dependence graph Cholesky decomposition LU decomposition QR decomposition Parallel Algorithms Design Signal Processing Systolic Algorithms Parallel Applications Commercial Applications for pipelined array computers

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Photoelectrochemical etching of GaN

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MRS Online Proceedings Library 1997年第1期468卷 349-354页

作者： C. Youtsey G. Bulman I. Adesida Microelectronics Laboratory and Dept. of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Urbana CREE Research Inc Durham

A photoelectrochemical etching process for n-type GaN using KOH solution and broad-area Hg arc lamp illumination is described. Etch rates as high as 320 nm/min are obtained. The etch rate is investigated as a function of light intensity for stirred and unstirred solutions. Preliminary results on etching of Al0.1Ga0.9N layers are reported.

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