Aiming at filtering irrelevant web services quickly and efficiently from a large collection, a kind of signature file, called Bit-Sliced Bloom-Filtered Signature (BBS). It is used as the index structure for web servic...
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Aiming at filtering irrelevant web services quickly and efficiently from a large collection, a kind of signature file, called Bit-Sliced Bloom-Filtered Signature (BBS). It is used as the index structure for web services discovery and composition. In addition, a successful business interaction of web services is checked with propositional logic statements. Furthermore, a reasonable solution to construct a Service Dependency Graph (SDG) to capture the input/output dependencies among the web services is also proposed. Compared with the inverted index approach, the BBS approach is quicker and more efficient based on experiments.
A reconfigurable system-on-chip (rSoC) architecture incorporating embedded uClinux operating system and multiple co-processing nodes has been reported (Williams and Bergmann, 2004). Our paper extends this platform to ...
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A reconfigurable system-on-chip (rSoC) architecture incorporating embedded uClinux operating system and multiple co-processing nodes has been reported (Williams and Bergmann, 2004). Our paper extends this platform to incorporate transparent management of reconfigurable hardware resources. This provides a convenient and flexible means for rapid application development of rSoC systems. The co-processor allocation and task management system is described. Details of the implementation are also included
In this paper, we deal with the problem of function approximation from a given set of input/output data. This problem consists of analyzing these training examples so that we can predict the output of the model given ...
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In this paper we propose a new technique focused on the search of new architectures for modelling complex systems in function approximation problems, in order to avoid the exponential increase in the complexity of the...
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Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit's performance and to increase designers' productivity. In this paper, we pre...
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作者：
Cai, YangAbascal, JulioCarnegie Mellon University
Ambient Intelligence Studio Cylab CIC 2218 4720 Forbes Avenue PittsburghPA15213 United States University of the Basque Country
Dept. of Computer Architecture & Technology School of Informatics Laboratory of Human-Computer Interaction for Special Needs Manuel Lardizabal 1 Donostia20018 Spain
Recent advances in arrays of microelectrodes open the door to both better understanding of the way the brain works and to the restoration of damaged perceptive and motor functions. In the case of sensorial inputs, dir...
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This paper presents an analysis of the behaviour of Consolidated Trees, CT (classification trees induced from multiple subsamples but without loss of explaining capacity). We analyse how CT trees behave when used to s...
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In real world problems solved with machine learning techniques, achieving small error rates is important, but there are situations where an explanation is compulsory. In these situations the stability of the given exp...
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Two architectures for parallel-prefix modulo 2n - 1 adders are presented in this paper. For large wordlengths we introduce the sparse modulo 2n - 1 adders that achieve significant reduction of the wiring complexity wi...
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ISBN:
(纸本)9789972611001
Two architectures for parallel-prefix modulo 2n - 1 adders are presented in this paper. For large wordlengths we introduce the sparse modulo 2n - 1 adders that achieve significant reduction of the wiring complexity without imposing any delay penalty. Then, the Ling-carry formulation of modulo 2n - 1 addition is presented. Ling modulo adders save one logic level of implementation and provide high-speed solutions for smaller adder widths, where wiring complexity is small. The performance of the proposed adders has been validated with static CMOS implementations. In all examined cases, the proposed designs achieve significant savings in both area and delay compared to previously published architectures.
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