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共 117 条记录，以下是81-90 订阅

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An efficient predictive admission control policy for heterogenous wireless bandwidth allocation in next generation mobile networks

An efficient predictive admission control policy for heterog...

引用

2006 International Wireless Communications and Mobile Computing Conference, IWCMC 2006

作者： Ali, Racha Ben Pierre, Samuel Mobile Computing and Networking Research Laboratory Dept. of Computer Engineering Ecole Polytechnique Montreal Montreal QC Canada

ISBN: (纸本)1595933069

Next generation mobile networks (NGMN) are expected to integrate several heterogenous wireless technologies in order to provide high system capacity and cost effective global service coverage. In this paper we propose an efficient predictive admission control policy for heterogenous wireless bandwidth allocation. We predict well chosen traffic parameters using neural networks and we estimate blocking probabilities using generally distributed traffic models. Furthermore, we use a Tabu search algorithm to find the optimal guard band for a multi-layer heterogenous NGMN. The objective of our multi-layer predictive admission control policy (MLPAC) is to minimize global blocking probability while guaranteeing a hard constraint on handoff dropping probability. It extends the overflow scheme used in two-layer hierarchical cellular systems (HCS) to multiple heterogenous access technologies in NGMN. Presented results show that our MLPAC approach is more efficient in allocating the scarce heterogenous wireless bandwidth to a higher number of accepted connections while maintaining minimal guard bands for horizontal and vertical handoff protection. Copyright 2006 ACM.

关键词： Wireless networks

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Formal verification of analog and mixed signal designs: Survey and comparison

Formal verification of analog and mixed signal designs: Surv...

引用

4th International IEEE North-East Workshop on Circuits and Systems, NEWCAS 2006

作者： Zaki, Mohamed H. Tahar, Sofiène Bois, Guy Dept. of Electrical and Computer Engineering Concordia University 1455 de Maisonneuve W. Montreal Que. H3G 1M8 Canada Genie Informatique Ecole Polytechnique de Montreal 5255 Avenue Decelles Montreal Que. H3T 2B1 Canada

ISBN: (纸本)1424404177

Analog and mixed signal (AMS) circuits are important integrated circuits that are usually needed at the interface between the electronic system and the real world. In contrast to digital designs, verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches. © 2006 IEEE.

关键词： Signal analysis

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A practical approach for monitoring analog circuits

A practical approach for monitoring analog circuits

引用

GLSVLSI'06 - 2006 ACM Great Lakes Symposium on VLSI

ISBN: (纸本)1595933476

Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog and mixed signal systems is a challenging task that requires lots of expertise and deep understanding of their behavior. In this paper, we present a run-time verification methodology based on monitoring the behavior (solution flow) of analog circuits. Monitors are deterministic timed automata that can be synthesized from temporal properties. For illustration purposes, we applied our methodology on the verification of the oscillation property of a tunnel diode oscillator. Copyright 2006 ACM.

关键词： Analog computers

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Abstraction based verification of analog circuits using computer algebra and constraint solving 9

Abstraction based verification of analog circuits using comp...

引用

9th International Workshop on Symbolic Methods and Applications to Circuit design, SMACD 2006

作者： Zaki, Mohamed H. Tahar, Sofiène Bois, Guy Dept. of Electrical and Computer Engineering Concordia University 1455 de Maisonneuve W. MontrealQCH3G 1M8 Canada Genie Informatique Ecole Polytechnique de Montreal Succ. Centre-Ville C.P. 6079 MontrealQCH3C 3A7 Canada

ISBN: (纸本)9788884535092

Formal methods have been advocated for the verification of digital designs where correctness is proved mathematically. Unlike its digital counterpart, analog and mixed-signal (AMS) systems verification is a challenging and exhaustive task that requires lots of expertise and deep understanding of their behavior. In this paper, we propose an abstraction methodology for the verification of safety properties of a class of non linear analog circuits described by polynomial differential equations. The method is based on combining techniques from constraint solving and com- puter algebra. For illustration purposes, we have used the computer algebra system Maple and the constraint solvers RealPaver and Rsolver to analyze the behavior of a non linear oscillator circuit.

关键词： Timing circuits

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design exploration with an application-specific instruction-set processor for ELA deinterlacing

Design exploration with an application-specific instruction-...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： M. Mbaye D. Lebel N. Belanger Y. Savaria S. Pierre Department of Electrical Engineering Ecole Polytechnique de Montrèal Montreal QUE Canada Dept. of Electrical Engineering Dept. of Computer Engineering École Polytechniquede Montréal Station Centre-Ville Montréal Canada

Achievable performance gains, when accelerating applications using ASIPs, with a good sequence of specialized instructions, depends on the applications' available parallelism, and possibilities for optimizations and transformations. The type and number of operations, and the number of data transfers of the application are also critical factors. Much progress has been done on ASIP customized instruction-identification and selection research; they are usually based on operation clustering. In this paper, we propose to minimize the number of data transfers during execution of specialized instructions sequence by storing temporary values in user-defined registers. The method avoids costly data transfers and allows parallel processing of demanding computations. This method is applied to the design of an ASIP dedicated to edge line average deinterlacing, an algorithm used in HDTV. Experimental results show that our design method applied to this application, yields a speedup factor larger than 18

关键词： Application specific processors Registers Acceleration Parallel processing Hardware Costs Application software Performance gain Clustering algorithms Arithmetic

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Accommodating usability driven changes in existing software architecture

Accommodating usability driven changes in existing software ...

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Proceedings of the Eighth IASTED International Conference on software engineering and Applications

作者： Rafla, Tamer Oketokoun, Rafiou Wiklik, Artur desmarais, Michel Robillard, Pierre-N. Software Engineering Research Lab. Department of Computer Engineering Ecole Polytechnique de Montreal Station Centre-Ville Montreal H3C 3A7 Canada

ISBN: (纸本)0889864276

Issues such as whether a product is easy to learn, to use, and whether the user can efficiently complete tasks using it, may greatly affect a product's acceptance in the marketplace. In software engineering, the support for usability is widely believed to be independent of software architecture design. This belief stems from the efforts to separate the user interface component from the application's internal logic, thus enabling changes to the interface without affecting the software architecture. This assumption has been recently challenged by Bass et al. who argue that architectural patterns must be in place in order to support good usability design. We investigate the degree to which this revised belief is true with a case study on the redesign of an existing application for better supporting usability. The redesign is based on implementing a task-oriented interface and help system. Preliminary results show that much, though not all, of the required changes can be done without major changes to the software architecture of GIMP. The results do support the idea that the envisioned usability redesign could not easily be implemented without some powerful architectural features that do not necessarily correspond to the specific patterns identified by Bass et al.

关键词： computer software

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Blocking probability analysis in future wireless networks

Blocking probability analysis in future wireless networks

引用

IEEE International Conference on Communications (ICC)

作者： R. Beaubrun S. Pierre J. Conan Department of Computer Science and Software Engineering Université LAVAL QUE Canada Mobile Computing and Networking Research Laboratory (LARIM) Ecole Polytechnique de Montrèal Montreal Canada

This paper proposes to model each cell of future wireless networks as a G/G/c/c queueing system. As such a model has not been explicitly addressed in the literature, we apply maximum entropy principles to evaluate both traffic distribution and blocking probability within each cell. Analysis of numerical results enables to specify the conditions under which the system offers good quality of service in terms of blocking probability. More specifically, such an analysis reveals that coefficient of variation of call arrivals has more impact over the blocking probability than coefficient of variation of channel holding time.

关键词： Intelligent networks Wireless networks Telecommunication traffic Traffic control Quality of service Mobile communication Entropy Context modeling computer science software engineering

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Toward nanorobotics platforms for high-throughput biomedical applications at the nanometer-scale

Toward nanorobotics platforms for high-throughput biomedical...

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Annual International Conference of the IEEE engineering in Medicine and Biology Society (EMBC)

作者： S. Martel J. Pelletier A. Frechette A. Azar B. Valin F. Poulin A. Blouin H. Prud'Hommne I. Hunter Department of Mechanical Engineering Massachusetts Institute of Technology USA Department of Computer Engineering Campus of University of Montréal Canada Canada Research Chair in Conception Fabrication and Validation of Micro/Nanosystems Polytechnique Montreal Montreal QC CA Dept. of Comput. Eng. Ecole Polytech. de Montreal Que. Canada

A new nanorobotics platform under development and which could be used for high-throughput biomedical applications at the nanometer-scale is briefly described. Each platform is based on a fleet of approximately 100 miniature autonomous instrumented robots, each capable of nanometer-scale operations. A central computer coordinates the operations of each miniature robot based on instructions received previously.

关键词： Nanobioscience Robot kinematics Instruments Nanotechnology Atomic force microscopy Application software Throughput Biomedical computing computer aided instruction DNA

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Variable resolution CMOS current mode active pixel sensor

Variable resolution CMOS current mode active pixel sensor

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： J. Coulombe M. Sawan C. Wang Electr. & Comput. Eng. Dept. Ecole Polytech. de Montreal Que. Canada Electrical and Computer Engineering Department Ecole Polytechnique de Montreal Montreal Canada Electrical and Computer Engineering Department Concordia University Montreal Canada

We present in this paper a current mediated active pixel sensor (APS) with variable image size and resolution for power saving, electronic zooming, and data reduction at the sensor level. The circuit can perform averaging of output signals in blocks of adjacent pixels (kernels) of size 1/spl times/1, 2/spl times/2 and 4/spl times/4, allowing data reduction without aliasing effects. To achieve this, a current approach is used, thus enabling high speed operation and low power supply capacity. A novel fixed pattern noise (FPN) reduction scheme using a compact circuitry is presented. The circuit compensates for pixel transconductance mismatch in addition to offset error via analog to digital conversion reference current scaling. Hspice simulations using parameters of a 0.35 /spl mu/m CMOS process illustrate the advantage of the new technique over usual correlated double sampling (CDS) in current mode sensors. Parallel integrated analog to digital converters (ADC), a data line-buffer and digital control complete the circuit making data transmission easy and simplifying hardware needed for using the image sensor.

关键词： Circuits Image sensors Signal resolution Analog-digital conversion CMOS image sensors Pixel Image resolution Kernel Power supplies Noise reduction

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Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Low power/low voltage high speed CMOS differential track and...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

关键词： Low voltage Latches delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process

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