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Speaker's Emotions Recognition Module Based on the GoogleLeNet Neural Network

Speaker's Emotions Recognition Module Based on the GoogleLeN...

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2022 International Conference on Smart Information systems and Technologies, SIST 2022

作者： Tereikovskyi, Ihor Tereikovska, Liudmyla Kryvoruchko, Olena Tereikovskyi, Oleh Tyshchenko, Dmytro Franchuk, Tamara National Technical University Of Ukraine Igor Sikorsky Kyiv Polytechnic Institute Dept. Of System Programming And Specialized Computer Systems Kyiv Ukraine Kyiv National University Of Construction And Architecture Dept. Of Information Technology For Design And Applied Mathematics Kyiv Ukraine Kyiv National University Of Trade And Economics Dept. Of Software Engineering And Cyber Security Kyiv Ukraine National Technical University Of Ukraine Igor Sikorsky Kyiv Polytechnic Institute Dept. Of Department Of Computer Engineering Kyiv Ukraine

ISBN: (数字)9781665467902

ISBN: (纸本)9781665467902

The article is devoted to the development of means for recognition of the emotions of the speaker, based on the neural network analysis of fixed fragments of the voice signal. The possibility of improving recognition tools through the use of a convolutional neural network of the GoogLeNet type is shown. The expediency of training the network on the examples of the TESS database is determined. A procedure for representing a voice signal in the form of a square grayscale image has been developed. Based on the use of the specified database, the modification of the GoogLeNet network was carried out. The architecture and software implementation of the recognition module have been developed. With the help of computer experiments, it has been established that after 150 epochs of training on a fairly limited training sample, the modified GoogLeNet makes it possible to achieve an accuracy of recognition of the speaker's emotions of approximately 0.97 on test examples. The obtained accuracy is comparable to the accuracy of the best modern systems of this purpose and confirms the promise of using neural network models like GoogLeNet for emotion recognition based on voice signal analysis. The need for further research aimed at reducing the resource intensity of the neural network model is shown. © 2022 IEEE.

关键词： Emotion Recognition

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Decentralized generation of multiple, uncorrelatable pseudonyms without trusted third parties

Decentralized generation of multiple, uncorrelatable pseudon...

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Lecture Notes in computer Science

作者： Lehnhardt, Jan Spalka, Adrian CompuGroup Medical Software GmbH Dept. of Data Security and System Architecture Maria Trost 23 Koblenz 56070 Germany University of Bonn Dept. of Computer Science III Römerstr. 164 53117 Bonn Germany

ISBN: (纸本)9783642228896

Regarding the increasing number of applications provided as external services, the importance of pseudonymous data as a means for privacy protection of user entities is growing. Along with it grows the relevance of secure and accurate generation, use and management of pseudonyms. In particular we consider the involvement of third parties in this process as potentially harmful, and therefore favor a decentralized pseudonym generation approach where the role of central components is reduced to a minimum. In this paper, we propose a pseudonym generation mechanism and focus on its implementation based on elliptic curve cryptography, in which every user entity can generate an arbitrary number of uncorrelatable pseudonyms with minimal effort, initially as well as at any later point in time. Because no sensitive information necessary for pseudonym generation is available on central components, our approach provides security as well as flexibility and usability. © 2011 Springer-Verlag.

关键词： Public key cryptography

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S3A: Secure system simplex architecture for enhanced security and robustness of cyber-physical systems

S3A: Secure system simplex architecture for enhanced securit...

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2013 2nd ACM International Conference on High Confidence Networked systems, HiCoNS 2013, as Part of CPSWeek 2013

作者： Mohan, Sibin Bak, Stanley Betti, Emiliano Yun, Heechul Sha, Lui Caccamo, Marco Information Trust Institute University of Illinois Urbana IL 61802 United States Dept. of Computer Science University of Illinois Urbana IL 61802 United States System Programming Research Group University of Rome Tor Vergata Rome Italy

ISBN: (纸本)9781450319614

The recently discovered '***' worm has drastically changed the perception that systems managing critical infrastructure are invulnerable to software security attacks. Here we present an architecture that enhances the security of safety-critical cyber-physical systems despite the presence of such malware. Our architecture uses the property that control systems have deterministic real-time) execution behavior to detect an intrusion within 0.6 μs while still guaranteeing the safety of the plant. We also show that even if an attacker is successful (or gains access to the operating system's administrative privileges), the overall state of the physical system still remains safe. © 2013 ACM.

关键词： Real time systems

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Concept of an Optical Distance and Speed Sensor Using Novel Offsetless Spatial Frequency Filters in the Area of Functional Safety

Concept of an Optical Distance and Speed Sensor Using Novel ...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Frank Wasinski Werner Bonath Ubbo Ricklefs Josef Börcsök Michael Schwarz Eike Hahn Dept. of Electrical Engineering and Information Technology THM University of Applied Sciences Giessen Germany ICAS Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Optical speed sensors based on the spatial frequency filter method are a proven technology that offer high measurement accuracy over a wide speed range. Newly developed variants also enable measurements at very low speeds and increase the robustness of the method [1]. This makes the sensor very suitable for use in the area of functional safety. A measurement chain up to safety integrity level 3 (SIL3) should be feasible via a combination with a safety system on a chip (SoC) for evaluating the measurement data and an extension of the sensor module to include safety-related elements [2], [3]. By integrating the sensor at IC level, a compact overall solution is to be made possible. After the first successful tests with the safety SoC, further examinations of the measuring method with regard to functional safety are now necessary.

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Designing a Video-on-Demand system for a Brazilian High Speed Network

Designing a Video-on-Demand System for a Brazilian High Spee...

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International Conference on Distributed Computing systems Workshop

作者： L. Souza A. Ripoll X.Y. Yang P. Hernandez F. Cores Computer Architecture & Operating System Dept. Universitat Autonoma de Barcelona Spain

Despite the availability of video-on-demand (VoD) services in a number of cities around the world, the large-scale deployment of VoD services has not been widely explored due to economic constraints. The high complexity founded in these systems makes the design process very difficult. This study presents a VoD system design for a highspeed metropolitan network, based on ATM technology, located in Brazil. To accomplish this goal, we have utilized our own simulation-based tool for VoD design called VODSim. This tool allows VoD research on any VoD platform, simulating the complete flow path followed by requests from clients to servers passing through the network infrastructure, allowing the configuration and tuning of multiple system parameters. Using VODSim, we analyse possible VoD architectures for the proposal environment (i.e. Centralized-server, Independent-servers, One-level-proxies and Distributedservers), studying key-parameters that have influence in system design. Experimental results show that Distributed-server architecture is the one that adjusts better to the analyzed infrastructure, improving streaming capacity by 16%, 25% and 28% more than One-level-proxies, Centralized and Independent-servers respectively. Taking in account future growth in VoD system, the Distributed-server even provides an unlimited scalability through new local network incorporation and using P2P techniques.

关键词： High-speed networks Network servers Computational modeling computer architecture Large-scale systems Proposals Analytical models Contracts Tin Operating systems

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On reducing both shift and capture power for sean-based testing

On reducing both shift and capture power for sean-based test...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Li, Jia Xu, Qiang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture ICT Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100080 China Dept. of Computer Science and Engineering Chinese University of Hong Kong Hong Kong Center for Intelligent System and Biomimetics Institute of Advanced Integration Technology CAS/CUHK Shenzhen 518067 China

ISBN: (纸本)9781424419227

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology. ©2008 IEEE.

关键词： Filling

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Evaluating dynamics and bottlenecks of memory collaboration in cluster systems 12

Evaluating dynamics and bottlenecks of memory collaboration ...

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12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing, CCGrid 2012

作者： Samih, Ahmad Wang, Ren Maciocco, Christian Tai, Tsung-Yuan Charlie Duan, Ronghui Duan, Jiangang Yan, Solihin Dept. of Electical and Computer Engineering North Carolina State University Raleigh NC United States System Architecture Lab. Intel Labs. Hillsboro OR United States Software and Services Group Intel Corp. Shanghai China

ISBN: (纸本)9780769546919

With the fast development of highly-integrated distributed systems (cluster systems), designers face interesting memory hierarchy design choices while attempting to avoid the notorious disk swapping. Swapping to the free remote memory through Memory Collaboration has demonstrated its cost-effectiveness compared to over provisioning the cluster for peak load requirements. Recent memory collaboration studies propose several ways on accessing the under-utilized remote memory in static system configurations, without detailed exploration of the dynamic memory collaboration. Dynamic collaboration is an important aspect given the run-time memory usage fluctuations in clustered systems. Further, as the interest in memory collaboration grows, it is crucial to understand the existing performance bottlenecks, overheads, and potential optimization. In this paper we address these two issues. First, we propose an Autonomous Collaborative Memory system (ACMS) that manages memory resources dynamically at run time to optimize performance. We implement a prototype realizing the proposed ACMS, experiment with a wide range of real-world applications, and show up to 3x performance speedup compared to a non-collaborative memory system without perceivable performance impact on nodes that provide memory. Second, we analyze, in dept., the end-to-end memory collaboration overhead and pinpoint the corresponding bottlenecks. © 2012 IEEE.

关键词： Cost effectiveness

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MeToo: Stochastic Modeling of Memory Traffic Timing Behavior

MeToo: Stochastic Modeling of Memory Traffic Timing Behavior

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： Yipeng Wang Ganesh Balakrishnan Yan Solihin Dept. of Electrical and Computer Engineering NC State University Memory System Architecture and Performance Advanced Micro Devices

The memory subsystem (memory controller, bus, andDRAM) is becoming a bottleneck in computer system performance. Optimizing the design of the multicore memory subsystem requires good understanding of the representative workload. A common practice in designing the memory subsystem is to rely on trace simulation. However, the conventional method of relying on traditional traces faces two major challenges. First, many software users are apprehensive about sharing their code (source or binaries) due to the proprietary nature of the code or secrecy of data, so representative traces are sometimes not available. Second, there is a feedback loop where memory performance affects processor performance, which in turnalters the timing of memory requests that reach the bus. Such feedback loop is difficult to capture with traces. In this paper, we present MeToo, a framework for generating synthetic memory traffic for memory subsystem design exploration. MeToo uses a small set of statistics that summarizes the performance behavior of the original applications, and generates synthetic traces or executables stochastically, allowing applications to remain proprietary. MeToo uses novel methods for mimicking the memory feedback loop. We validate MeToo clones, and show very good fit with the original applications' behavior, with an average error of only 4.2%, which is a small fraction of the errors obtained using geometric inter-arrival(commonly used in queueing models) and uniform inter-arrival.

关键词： Cloning Random access memory Feedback loop Timing Multicore processing Bandwidth Power demand

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Multi-vehicle Route Planning for Efficient Urban Freight Transport

Multi-vehicle Route Planning for Efficient Urban Freight Tra...

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International IEEE Conference on Intelligent systems, IS

作者： Petar Mrazovic Elif Eser Hakan Ferhatosmanoglu Josep L. Larriba-Pey Mihhail Matskin Dept. of Software and Computer System Royal Institute of Technology Stockholm Sweden Dept. of Computer Engineering Bilkent University Ankara Turkey Dept. of Computer Science University of Warwick Coventry United Kingdom Dept. of Computer Architecture Polytechnic University of Catalonia Barcelona Spain

ISBN: (纸本)9781538670989;9781538670972

The urban parking spaces for loading/unloading are typically over-occupied, which shifts delivery operations to traffic lanes and pavements, increases traffic, generates noise, and causes pollution. We present a data analytics based routing optimization that improves the circulation of vehicles and utilization of parking spaces. We formalize this new problem and develop a novel multivehicle route planner that avoids congestions at loading/unloading areas and minimizes the total duration. We present the developed tool with an illustration and analysis for the urban freight in the city of Barcelona, which monitors tens of thousands of deliveries every day. Our system includes an effective evaluation of candidate routes by considering the waiting times and further delays of other deliverers as a first class citizen in the optimization. A two-layer local search is proposed with a greedy randomized adaptive method for variable neighborhood search. Our approach is applied and validated over data collected across Barcelona's urban freight transport network, which contains 3,704,034 parking activities. Our solution is shown to significantly improve the use of available parking spaces and the circulation of vehicles, as evidenced by the results. The analysis also provides useful insights on how to manage delivery routes and parking spaces for sustainable urban freight transport and city logistics.

关键词： Loading Optimization Planning Routing Urban areas Roads Load modeling

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Design of power-efficient FPGA convolutional cores with approximate log multiplier 27

Design of power-efficient FPGA convolutional cores with appr...

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27th European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning, ESANN 2019

作者： Oliveira, Leonardo Tavares Kim, Min Soo Del Barrio, Alberto A. Bagherzadeh, Nader Menotti, Ricardo Universidade Federal de São Carlos Departamento de Computação Rod. Washington Luís Km 235 Brazil University of California Irvine Dept. of Electrical Engineering and Computer Science 5200 Engineering Hall United States Complutense University of Madrid Dept of Computer Architecture and System Engineering Ciudad Universitaria Plaza Ciencias Spain

ISBN: (纸本)9782875870650

This paper presents the design of a convolutional core that utilizes an approximate log multiplier to significantly reduce the power consumption of FPGA acceleration of convolutional neural networks. The core also exploits FPGA reconfigurability as well as the parallelism and input sharing opportunities in convolutional layers to minimize the costs. The simulation results show reductions up to 78.19% of LUT usage and 60.54% of power consumption compared to the core that uses exact fixed-point multiplier, while maintaining comparable accuracy on a subset of MNIST dataset. © 2019 ESANN (***). All rights reserved.

关键词： Field programmable gate arrays (FPGA)

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