Abstraction is a basic foundation and a powerful means in science and engineering, such as philosophy, mathematics, cognitive informatics, computing, and softwareengineering, because any complex inference process is ...
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As technology is used to support team-based activities, one important factor affecting the performance of teams is the kind of mental model shared between team members. This paper describes a novel conceptual graph ba...
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ISBN:
(纸本)9781605583549
As technology is used to support team-based activities, one important factor affecting the performance of teams is the kind of mental model shared between team members. This paper describes a novel conceptual graph based methodology to study these mental models to better understand how shared mental models affect performance and other factors of a team's behavior. Copyright 2008 ACM.
Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA...
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ISBN:
(纸本)9781424428205
Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. A new topological representation called Ordered Quadtree is then custom-made for this basic idea to facilitate its integration into SA iterations. After the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in SA process. Experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than Parquet. Besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. At last, Local Refinement is also adopted to guide the SA process and reshape soft modules to meet the constraint on their aspect ratios (ARs). With its help, SAFFOA can still generate feasible floorplans with no deadspace under a strict AR constraint such as [0.5,2].
This paper presents an algorithm that permits the identification of apneas - cessations in the sleeping patient's respiratory flow - in the respiratory airflow signal and relates them to the drops in blood oxyhemo...
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Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, traditional profiling on individual proces...
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ISBN:
(纸本)9781605584706
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, traditional profiling on individual processors cannot capture useful execution information to assist software optimization. A new method to model parallel executions of interacting programs is needed. In this paper, we consider the software optimization problem for throughput-constrained MPSoC designs. We define the "longest delay path" as a sequence of steps leading to a throughput constraint violation and propose an algorithm to build up the path dynamically during simulation. Using an industrial-strength MPEG-2 decoder design in our case study and custom instructions for software optimization, we show that we can optimize the software efficiently in MPSoC designs using frequently executed statement information from the longest delay path. Copyright 2008 ACM.
In unattended or hostile environment like battlefield, sensor nodes may be compromised. If one node is compromised, group key which is shared by all the group members should be rekeyed in real-time and the compromised...
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In this paper, we describe a protocol stack to enable communication between biological nano scale (bio-nano) devices. We identify key design considerations and protocol components and suggest suitable molecular comput...
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Document binarization is an active research area for many years. There are many difficulties associated with satisfactory binarization of document images and especially in cases of degraded historical documents. In th...
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In this paper, we study the use of iterative multiuser detectors for co-channel interference suppression in wireless cellular systems. We demonstrate that a receiver with a single receive antenna is capable of detecti...
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In this paper, we study the use of iterative multiuser detectors for co-channel interference suppression in wireless cellular systems. We demonstrate that a receiver with a single receive antenna is capable of detecting and cancelling a single in-band interferer that uses the same coding and modulation scheme as the desired signal. We investigate the benefits of using such an interference canceller in the mobile receiver in the downlink scenario of a two-hop relay network. Results show significant improvements with iterative interference cancellation in terms of the average system throughput and outage probability. Because the interference canceller is so effective, more aggressive frequency reuse schemes can be now considered, such as using smaller cluster sizes, using 3-sectored cells where all sectors share the same frequency band, and using non-orthogonal channels for relaying.
DEVS is a formal modeling and simulation (M&S) frame-work that supports hierarchical, modular model composition. DEVS-based M&S environments have been used successfully to understand, analyze, and develop a va...
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DEVS is a formal modeling and simulation (M&S) frame-work that supports hierarchical, modular model composition. DEVS-based M&S environments have been used successfully to understand, analyze, and develop a variety of systems. As the systems under study become more large and complex, performance of the simulator becomes critical. Nevertheless, evaluating the operation of such simulators is a complex process. We present DEVStone, a synthetic benchmark devoted to automate the evaluation of DEVS- based simulators, which generates models with varied structure and behavior. DEVStone was used to study the efficiency of different simulation engines provided by the CD++ toolkit, this results were later compared with similar results on ADEVS with a demanding set of experiments, enabling thorough performance analysis. DEVStone facilitates performance analysis for successive versions (e.g.. upgrades or fixes) of the same simulation engine, and provides a common metric to compare different M&S environments.
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