The last six years has seen Moore's Law continue to produce incredible gains in computational power. Indeed, the November, 2007 list of the top ten fastest supercomputers in the world contained no machines with ac...
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A tactic manager which can change the behavior of a simulation model according to the tactics defined outside of the model has been studied and implemented. Based on DEVS(discrete event system specification) formalism...
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To improve trapping using deeper well AlGaN (Χ=3.8eV), lower voltage drop in high-κ AlLaO3 barrier (κ=23), and smaller erase current by large ΔEc of AlLaO3/TaN, the SiO 2/AlGaN/AlLaO3/TaN devices show good 85°...
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Research questionnaire was carried on the usage of housing equipment focusing on the continuous ventilation system in apartmenthouses. It was confirmed that ventilation systems are operated 24 hours more than 80% of t...
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Research questionnaire was carried on the usage of housing equipment focusing on the continuous ventilation system in apartmenthouses. It was confirmed that ventilation systems are operated 24 hours more than 80% of the respondents, and the operating ratio increases as the household number *** the other hand, the ratio of opening outdoor air inlets for ventilation system was as low as about 50%. Cross correlation analysis showed that the operation of continuous ventilation system is effective in suppressing dew condensation, mold and bad smell, and the majority of respondents evaluate the ventilation system satisfactorily. Separate analysis by age revealed that aged households are very sensitive on utilities expense and tend to apply local heating of a room and bathing is not frequent.
This paper proposes an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by efficiently recovering energy from the bit/word line capacitors. Powered by a single-phase s...
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This paper proposes an energy-recovering (a.k.a. adiabatic) static RAM with a novel driver that reduces power dissipation by efficiently recovering energy from the bit/word line capacitors. Powered by a single-phase sinusoidal power-clock, our SRAM delivers read and write operations with single-cycle latency. To that end, a precharge-low scheme is employed along with a modified sense amplifier design that achieves high efficiency at differential voltages near VSS. A simple control circuit is used to maintain driver operation in synchrony with the power-clock waveform. Feedback circuitry from the driver output to the control circuit ensures that our driver remains efficient, independent of the access pattern. Our energy recovering SRAM functions correctly while achieving substantial energy savings over a wide range of supply voltages and operating frequencies. Hspice simulations of a simple full-custom adiabatic 256×256 SRAM, that includes the energy recovering bit/word line drivers, the cell array, and the sense amplifiers, show over 2.6x energy savings at 3V, 300MHz in comparison with its conventional counterpart.
Bivalirudin is a direct thrombin inhibitor used in the cardiac intensive care unit in patients who develop an allergic reaction to heparin. Since it is not a commonly used drug, clinical experience with its dosing is ...
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The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, re...
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ISBN:
(纸本)1581134614
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often consist of long interconnect wires, resulting in large area and high power consumption. In this paper, we propose a data-transfer oriented design methodology to implement a low-power 256-state rate-1/3 IS95 Viterbi decoder. Our architectural level scheme uses operation partitioning, packing, and scheduling to analyze and optimize interconnect effects in early design stages. In comparison with other published Viterbi decoders, our approach reduces the global data transfers by up to 75% and decreases the amount of global buses by up to 48%, while enabling the use of deeply pipelined datapaths with no data forwarding. In the RTL implementation of the individual processors, we apply precomputation in conjunction with saturation arithmetic to further reduce power dissipation with provably no coding performance degradation. Designed using a 0.25 μm standard cell library, our decoder achieves a throughput of 20 Mbps in simulation and dissipates only 450 mW.
A novel microstrip line layout is developed to direct measure the min. noise figure (NFmin) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NFmin of 1.05 dB at 10 GHz is...
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We demonstrate a dislocation-free InAlAs/InGaAs/InAlAs-on-Insulator (IIIVOI) HEMT on a Si substrate, which has a high drain current and 8,100 cm2/Vs mobility. To reduce the Schottky gate leakage current in the device,...
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A new concept for detection of human faces is presented. An efficient approach to reduce the computation time taken by neural networks for the searching process is introduced. We combine both Fourier and wavelet trans...
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