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Configuring Role-Based Access Control to Enforce Mandatory and Discretionary Access Control Policies

ACM Transactions on Information and System Security 2000年第2期3卷 85-106页

作者： Osborn, Sylvia Sandhu, Ravi Munawer, Qamar Dept. of Computer Science The University of Western Ontario London ON N6A 5B7 Canada Laboratory for Information Security Technology MS4A4 Information and Software Engineering Department George Mason University Fairfax VA 22030 United States

Access control models have traditionally included mandatory access control (or lattice-based access control) and discretionary access control. Subsequently, role-based access control has been introduced, along with claims that its mechanisms are general enough to simulate the traditional methods. In this paper we provide systematic constructions for various common forms of both of the traditional access control paradigms using the role-based access control (RBAC) models of Sandhu et al., commonly called RBAC96. We see that all of the features of the RBAC96 model are required, and that although for the mandatory access control simulation, only one administrative role needs to be assumed, for the discretionary access control simulations, a complex set of administrative roles is required. © 2000, ACM. All rights reserved.

关键词： discretionary access control lattice-based access control Management mandatory access control Role-based access control Security

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Size versus robustness in evolved sorting networks: is bigger better?

Size versus robustness in evolved sorting networks: is bigge...

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NASA/DoD Workshop on Evolvable Hardware

作者： J. Masner J. Cavalieri J.F. Frenzel J. Foster Center for Secure and Dependable Software Dept. of Computer Science University of Idaho Dept. of Electrical Engineering Micro electronics Research and Communications Institute University of Idaho

We are interested in discovering how and why circuits developed using evolutionary methods tend to be more robust than hand designed ones. To this end, we compare evolved circuits to known, minimal sorting networks. We introduce a new, size-independent metric, called bitwise stability (BS), which measures how well a network performed when subjected to real-world types of errors. In particular, we examine stuck-on-one, stuck-on-zero and passthrough errors, a generalization of a short circuit. Networks were evolved using tree structured and linear encoded chromosomes. We found that evolution improves bitwise stability and that tree structures tend to confer more bitwise stability than linear structured chromosomes. We discuss how the size of a sorting network affects its robustness and our discovery that bigger does not necessarily mean better.

关键词： Robustness Intelligent networks Sorting Hardware computer science Circuit stability Biological cells Encoding Microelectronics Circuit faults

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Special purpose image convolution with evolvable hardware

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EvoWorkshops 2000: 2nd European Workshop on Evolutionary Computation in Image Analysis and Signal Processing, EvoIASP 2000, 1st European Workshop on Evolutionary Computation in Systems, Control and Drives in Industry, Evo-SCONDI 2000, 2nd European Workshop on Evolutionary Telecommunications, EvoTel 2000, 1st European Workshop on Evolutionary Scheduling and Timetabling, EvoStim 2000, 3rd European Workshop on Evolutionary Robotics, EvoRob 2000 and 1st European Workshop on Evolutionary Aeronautics, EvoFlight 2000 held in conjunction with European Conference on Genetic Programming, EuroGP 2000 and 3rd International Conference on Evolvable Systems, ICES 2000

作者： Dumoulin, Joe Foster, James A. Frenzel, James F. McGrew, Steve New Light Industries Ltd SpokaneWA United States Center for Secure and Dependable Software U. Idaho MoscowID United States Microelectronics Research and Communications Inst U. Idaho MoscowID United States Dept. of Computer Science U. Idaho MoscowID United States Dept. of Electrical and Computer Engineering U. Idaho MoscowID United States

ISBN: (纸本)3540673539

In this paper, we investigate a unique method of inventing linear edge enhancement operators using evolution and reconfigurable hardware. We show that the technique is motivated by the desire for a totally automated object recognition system. We show that an important step in automating object recognition is to provide flexible means to smooth images, making features more obvious and reducing interference. Next we demonstrate a technique for building an edge enhancement operator using evolutionary methods, implementing and testing each generation using the Xilinx 6200 family FPGA. Finally, we present the results and conclude by mentioning some areas of further investigation. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Object recognition

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A method to derive application-specific embedded processing cores 00

A method to derive application-specific embedded processing ...

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Proceedings of the eighth international workshop on Hardware/software codesign

作者： Olivier Hébert Ivan C. Kraljic Yvon Savaria Electrical and Computer Engineering Dept. École Polytechnique de Montréal Montréal Qc Canada MiroTech MicroSystems Inc. Saint-Laurent Qc Canada Electrical and Computer Engineering Dept. École Polytechnique de Montréal Montréal Qc Canada and MiroTech MicroSystems Inc. Saint-Laurent Qc Canada

ISBN: (纸本)9781581132687

The concept of system-on-a-chip is becoming increasingly popular for the integration of complex systems. New types of processor cores are now available that enable the designer to customize their processors for the target applications. These soft cores are not tightly coupled with the target application, and this leads to processing cores sub-optimal for their specific applications. This paper proposes a method to derive application-specific embedded processors from soft processor cores. The derivation process involves an analysis of the resources of the processing core used by the target application. Then a series of optimizations based on the analysis results are performed on an optimizable model of the processor core. We present the tool used to perform the analysis of the resources used by an application, and results from a real-world case. Then, various optimization methods are described.

关键词： configurable processor system-on-a-chip soft core embedded core custom core

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Efficient Specialisation in Prolog Using the Hand-Written Compiler Generator LOGEN

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Electronic Notes in Theoretical computer Science 2000年第2期30卷 157-162页

作者： Michael Leuschel Jesper Jørgensen Declarative Systems and Software Engineering Dept. of Electronics and Computer Science University of Southampton Southampton SO17 1BJ UK Dept. of Mathematics and Physics Royal Veterinary and Agricultural University Thorvaldsensvej 40 DK-1871 Frederiksberg C Denmark

The so called “ cogen approach” to program specialisation, writing a compiler generator instead of a specialiser, has been used with considerable success in partial evaluation of both functional and imperative languages. In earlier work we have shown that this approach is also applicable to partial evaluation of logic programming languages, also called partial deduction. In this paper we extend upon this by allowing partially instantiated datastructures (via binding types), which are especially important in the context of logic programming. We also extend cogen to directly support a large part of Prolog's declarative and non-declarative features and how semi-online specialisation can be efficiently integrated. Benchmarks show that the resulting cogen is very efficient, generates very efficient generating extensions (executing up to several orders of magnitude faster than current online systems) which in turn perform very good and non-trivial specialisation, even rivalling existing online systems.

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Path tracking control of tracked vehicles

Path tracking control of tracked vehicles

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IEEE International Conference on Robotics and Automation (ICRA)

作者： M. Ahmad V. Polotski R. Hurteau Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Department of Electrical and Computer Engineering Ecole Polytechnique Montreal Canada

A path tracking control algorithm for tracked surface drilling machines is presented. The general dynamic model of such vehicle is simulated including track-soil interactions. The controller is based on feedback linearization of the equations with feedforward friction compensation. It linearizes the complex force-slip relationship to relate the states of the system to the inputs. The controller based on simplified models is applied to the detailed simulated model of the vehicle. The result is an accurate control of the lateral offset and forward velocity error along a path.

关键词： Vehicle dynamics Force control Drilling machines Friction Velocity control Automatic control Remotely operated vehicles Equations Error correction Mobile robots

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Design and implementation of VoD server by using clustered file system

Design and implementation of VoD server by using clustered f...

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IEEE International Conference on Multimedia and Expo (ICME)

作者： Chang-Soon Park Mann-Ho Lee Young-Sung Son Oh-Young Kwon Dept. of Software Eng. ETRI Taejon South Korea Department of Computer Science Chungnam National University Taejon South Korea Software Engineering Department Electronics and Telecommunications Research Institute Taejon South Korea Department of Computer Engineering Korea University of Technology and Education ChungNam South Korea

We introduce the CROWN (Clustering Resources on Workstation Network) system that consists of several PCs interconnected with the Myrinet. In order to provide multimedia-on-demand services, especially VoD, we have developed CrownFS as a continuous media file system over the Linux operating system. CrownFS is a user level file system. Because the clustering technology is based on off-the-shelf commodities, user-level design and implementation can be natural in a clustering system and has a great benefit in portability. The architecture of CrownFS and its usage for VoD service are presented. Field test results show that a prototype CrownFS VoD server with four nodes can provide 150 MPEG-1 streams concurrently. CrownFS can also be extended to support a discrete media file system and to provide over a thousand multimedia streams.

关键词： File servers Streaming media File systems Network servers Workstations Personal communication networks Linux Operating systems Testing Prototypes

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Variable resolution CMOS current mode active pixel sensor

Variable resolution CMOS current mode active pixel sensor

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： J. Coulombe M. Sawan C. Wang Electr. & Comput. Eng. Dept. Ecole Polytech. de Montreal Que. Canada Electrical and Computer Engineering Department Ecole Polytechnique de Montreal Montreal Canada Electrical and Computer Engineering Department Concordia University Montreal Canada

We present in this paper a current mediated active pixel sensor (APS) with variable image size and resolution for power saving, electronic zooming, and data reduction at the sensor level. The circuit can perform averaging of output signals in blocks of adjacent pixels (kernels) of size 1/spl times/1, 2/spl times/2 and 4/spl times/4, allowing data reduction without aliasing effects. To achieve this, a current approach is used, thus enabling high speed operation and low power supply capacity. A novel fixed pattern noise (FPN) reduction scheme using a compact circuitry is presented. The circuit compensates for pixel transconductance mismatch in addition to offset error via analog to digital conversion reference current scaling. Hspice simulations using parameters of a 0.35 /spl mu/m CMOS process illustrate the advantage of the new technique over usual correlated double sampling (CDS) in current mode sensors. Parallel integrated analog to digital converters (ADC), a data line-buffer and digital control complete the circuit making data transmission easy and simplifying hardware needed for using the image sensor.

关键词： Circuits Image sensors Signal resolution Analog-digital conversion CMOS image sensors Pixel Image resolution Kernel Power supplies Noise reduction

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Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input

Low power/low voltage high speed CMOS differential track and...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： C.J.B. Fayomi G.W. Roberts M. Sawan Dept. of Electr. & Comput. Eng. Ecole Polytech. Montreal Que. Canada Microelectronics and Computer Systems Laboratory McGill University Montreal Canada Department of Electrical and Computer Engineering Ecole Polytechnique de Montreal Montreal Canada

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

关键词： Low voltage Latches Delay Rail to rail operation Transconductance Operational amplifiers Rail to rail amplifiers Circuit simulation CMOS digital integrated circuits CMOS process

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Parallel Problem Solving from Nature PPSN VI: 6th International Conference Paris, France, September 18-20, 2000 Proceedings 6th

Parallel Problem Solving from Nature PPSN VI: 6th Internatio...

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6th International Conference on Parallel Problem Solving from Nature, PPSN 2000

作者： Schoenauer, Marc Deb, Kalyanmoy Rudolph, Günter Yao, Xin Lutton, Evelyne Merelo, Juan Julian Schwefel, Hans-Paul CMAP Ecole Polytechnique Palaiseau Cedex France Indian Institute of Technology Kanpiir Dept. of Mechanical Engineering Kanpur Genetic Algorithms Laboratory Kanpur India Universität Dortmund Fachbereich Informatik Lehrstuhl für Systemanalyse Joseph-von-Fraunhofer-Str. 20 Dortmund Germany The University of Birmingham School of Computer Science Edgbaston Birmingham United Kingdom INRIA Rocquencourt Projet Fractales BP 105 Le Chesnay Cedex France Universidad de Granada s/n Dept. de Arquitectura y Technologa de los Computadores Campus Fuenetenueva Spain

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