The Graph Layout Toolkit is a family of portable graph drawing and layout libraries designed for integration into graphical user interface application programs. When visualizing graphs, it becomes essential to communi...
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XML users can make their own document structure and tagsets by freely defining the DTD with their intention. This freedom of defining tagsets and the structures, however, prevents the interchange of an XML document be...
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A multidatabase system provides integrated access to heterogeneous, autonomous component databases in a distributed system. In order to gain integrated access to a multidatabase system, semantic heterogeneities have t...
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This paper describes a new low-voltage low-power CMOS instrumentation amplifier used, among others, for biomedical applications. Since the nerve signal monitored with this amplifier has very low amplitude and low freq...
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This paper describes a new low-voltage low-power CMOS instrumentation amplifier used, among others, for biomedical applications. Since the nerve signal monitored with this amplifier has very low amplitude and low frequency, it is, at first fed to a low voltage chopper amplifier to reduce the flicker (1/f) noise then amplified with a new programmable, with high CMRR instrumentation amplifier. The design and the simulation results are presented. The layout is drawn in 0.35 /spl mu/m CMOS process with an active area of 0.145 mm/sup 2/. The preliminary test results are consistent with the simulation.
Recently, object-oriented (OO) frameworks have been known to be highly effective and practical for software reuse;as shown in San Francisco project, a large-scaled industry project for framework development. However, ...
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One of the most attractive features of computer-controlled systems should be the ease with which they can be modified to incorporate improvements and new capabilities. It would be desirable to make the software change...
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One of the most attractive features of computer-controlled systems should be the ease with which they can be modified to incorporate improvements and new capabilities. It would be desirable to make the software changes in a safe and reliable fashion while the system is running. The Simplex architecture, a real-time software technology developed at the Carnegie Mellon University softwareengineering Institute, is designed for this purpose. We introduce the basic structure of the Simplex architecture and describe the types of faults it can handle. We describe the fault detection mechanism based on the trajectories of the physical system in its state space, and derive the control switching logic that determines which controller is chosen to control the physical system in each sampling period.
Three types of adaptive multiscale moment methods, which are based on the wavelet-like basis, are presented here for analyzing electromagnetic scattering from perfectly conducting two-dimensional electrically large ob...
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Three types of adaptive multiscale moment methods, which are based on the wavelet-like basis, are presented here for analyzing electromagnetic scattering from perfectly conducting two-dimensional electrically large objects. The conducting structures are assumed to be in a free-space medium and is illuminated by a TM plane wave. The three algorithms decompose the conventional method of moment matrix into a scaled-block matrix through a matrix multiplication. The numbers of unknowns corresponding to the linear equations at increasing scales can be automatically reduced by using a suitable threshold and the solution obtained from previous scales. Numerical results for the monostatic radar cross section of several electrically large objects are presented. Comparison has been made with respect to the numerical solution obtained by the moment method. The objective of this paper is to illustrate that a possibility exist for efficiently reducing the size of the linear equations in an automatic fashion utilizing the adaptive multiscale moment methods.
This paper addresses how domain analysis served to help create reusable architectures and components in the development of a real-time embedded system. The resulting product is Motorola's FLEX™ Kernel, a set of co...
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We describe a system that supports source-level integration of ML-like functional language code with ANSI C or Ada83 code. The system works by translating the functional code into type-correct, 'vanilla' C or ...
We describe a system that supports source-level integration of ML-like functional language code with ANSI C or Ada83 code. The system works by translating the functional code into type-correct, 'vanilla' C or Ada;it offers simple, efficient, type-safe inter-operation between new functional code components and 'legacy' third-generation-language components. Our translator represents a novel synthesis of techniques including user-parameterized specification of primitive types and operators;removal of polymorphism by code specialization;removal of higher-order functions using closure datatypes and interpretation;and aggressive optimization of the resulting first-order code, which can be viewed as encoding the result of a closure analysis. Programs remain fully typed at every stage of the translation process, using only simple, standard type systems. Target code runs at speeds comparable to the output of current optimizing ML compilers, even though handicapped by a conservative garbage collector.
A fully integrated Phase Locked Loop (PLL) with wide lock range is presented in this paper. The designed structure of the PLL is based on the charge-pump type with a differential architecture Voltage Controlled Oscill...
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A fully integrated Phase Locked Loop (PLL) with wide lock range is presented in this paper. The designed structure of the PLL is based on the charge-pump type with a differential architecture Voltage Controlled Oscillator (VCO) building block. In the proposed VCO, current mirrors are used as the active load of the source-followers which allow a high stability of VCO oscillation within a wide control range. The PLL has been implemented in 0.8 /spl mu/m BiCMOS technology without the need of any external components. It operates with a lock range of 14 to 420 MHz. The lock time is 15 /spl mu/S. The resulting layout area and the power dissipation of the whole PLL are 0.65 mm/sup 2/ and 18 mW respectively.
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