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Structural and Compositional Evolution of Self-Assembled Germanium Islands on Silicon (001) During High Growth Rate LPCVD

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MRS Online Proceedings Library 2004年第1期775卷 9251-9256页

作者： Gabriela D. M. Dilliway Nicholas E. B. Cowern Chris Jeynes Lisa O’Reilly Patrick J. McNally Darren M. Bagnall Dept. of Electronics and Computer Science Univ. of Southampton Highfield UK Advanced Technology Institute Univ. of Surrey Guildford UK Research Institute for Networks & Communications Engineering (RINCE) School of Electronic Engineering Dublin City University Dublin 9 Ireland

Understanding the process of self-organization of Ge nanostructures on Si with controlled size distribution is a key requirement for their application to devices. In this study, we investigate the temporal evolution of self-assembled islands during the low pressure chemical vapour deposition (LPCVD) of Ge on Si at 650°C using high growth rates (6–9 nm/min). The islands were characterized by atomic force microscopy, transmission electron microscopy, Rutherford backscattering spectrometry and micro-Raman spectroscopy. We found that the first nanostructures to assemble were small islands, with a narrow size distribution, typical of the ‘lens-shaped’ structures reported in previous studies. Next to form were a population of larger ‘lens-shaped’ islands with a similar surface density to that of the small islands, but with broad height and width distributions. These islands differ from the pyramid-shaped islands previously reported for a similar size range. On further Ge deposition, the population evolves into one of large square-based truncated pyramids with a very narrow size distribution. Such pyramidal structures were previously reported at smaller sizes. Furthermore, we see no evidence of the multifaceted domes previously reported in this size range. The small ‘lens-shaped’ islands appear to be strained, whilst some of the intermediate-sized islands and all the large truncated pyramids contain misfit strain relaxation induced defects. Additionally, in the both the intermediate size ‘lens-shaped’ islands and in the large size truncated pyramidal islands, there is evidence of Si-Ge strain-induced alloying, more significant in the first than in the latter. Our observation of ‘lens shaped’ islands and truncated pyramids at larger sizes than are normally observed, suggests a kinetically driven process that delays the evolution of energetically favourable island structures until larger island sizes are reached.

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De-pipeline a software-pipelined loop

De-pipeline a software-pipelined loop

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2003 IEEE International Conference on Accoustics, Speech, and Signal Processing

作者： Su, Bogong Wang, Jian Hu, Erh-Wen Manzano, Joseph Dept. of Computer Science William Paterson Univ. of New Jersey Wayne NJ 07470 United States Wireless Speech and Data Processing Nortel Networks Montreal Que. H3E 1H6 Canada

Software pipelining is a loop optimization technique that has been widely implemented in modern optimizing compilers. In order to fully utilize the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining. However, because of the transformation of the original sequential code, a software-pipelined loop is often difficult to understand, test, and debug. It is also very difficult to reuse and port a software-pipelined loop to other processors especially when the original sequential code is unavailable. In this paper we propose a de-pipelining technique, which converts the optimized assembly code of a software-pipelined loop back to a semantically equivalent sequential counterpart. Preliminary experiments on 20 assembly programs verifies the validity of the proposed depipelining algorithm.

关键词： Digital signal processing

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Assembly code conversion through pattern mapping between two VLIW DSP processors: A case study 6

Assembly code conversion through pattern mapping between two...

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6th International Conference on Signal Processing, ICSP 2002

作者： Su, Bogong Wang, Jian Hu, Erh-Wen Manzano, Joseph Dept. of Computer Science William Paterson University of New Jersey WayneNJ07470 United States Wireless Speech and Data Processing Nortel Networks MontrealQCH3E 1H6 Canada

ISBN: (纸本)0780374886

In this paper, we investigate a new pattern mapping method to convert the assembly code between two VLIW digital signal processors. The method is so named because the pattern of the code is kept unchanged during the conversion process in order to manage complexity. As a case study, we first manually convert the assembly code of a typical DSP application from Texas Instruments' TIC62, the source processor, to a high level intermediate code. We then feed the intermediate code to the SCI40 compiler backend to generate the assembly code of the target SC140 processor, which is executed on the SC140 simulator. The result thus obtained compares favorably with that obtained directly by compiling and executing the C code on the SCI40 system in terms of both validity and total execution cycles. © 2002 IEEE.

关键词： Digital signal processors

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A scalable loop optimization approach for scalable DSP processors 25

A scalable loop optimization approach for scalable DSP proce...

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25th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2000

作者： Wang, Jian Su, Bogong Hu, Erh-Wen Wireless Speech and Data Processing Nortel Networks Montreal MontrealQCH3E 1H6 Canada Dept. of Computer Science William Paterson University of New Jersey WayneNJ07470 United States

ISBN: (纸本)0780362934

This paper proposes the possibility of reuse of the existing optimized DSP code on a scalable high-performance VLIW DSP processor. Since loops are the critical paths in most DSP applications, we focus on issues related to loop optimization. In our approach, we first perform a loop alignment transformation on the source level;we then reuse the existing optimized loop code on the assembly level. The approach is highly portable because it is independent of DSP hardware details. It can be used directly by a DSP programmer on the source level and/or by a DSP compiler designer to implement independent optimization modules. © 2000 IEEE.

关键词： Very long instruction word architecture

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Heterogeneous Simulation - Mixing Discrete-Event Models with dataflow

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Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 1997年第1-2期15卷 127-144页

作者： Chang, Wan-Teh Ha, Soonhoi Lee, Edward A. EECS Dept. U.C. Berkeley United States Department of Computer Engineering Seoul National University South Korea Elec. Eng. and Comp. Sci. Department University of California Berkeley CA United States National Taiwan University Taipei Taiwan Department of Computer Engineering Seoul National University South Korea Hyundai Electronics Indust. Corp. Seoul National University South Korea Elec. Eng. and Computer Sciences University of California Berkeley CA United States Elec. Eng. and Comp. Sci. Department U.C. Berkeley United States Yale University MIT United States University of California Berkeley CA United States Bell Telephone Laboratories Holmdel NJ United States Adv. Data Communications Laboratory Berkeley Design Technology Inc. United States

This paper relates to system-level design of signal processing systems, which are often heterogeneous in implementation technologies and design styles. The heterogeneous approach, by combining small, specialized models of computation, achieves generality and also lends itself to automatic synthesis and formal verification. Key to the heterogeneous approach is to define interaction semantics that resolve the ambiguities when different models of computation are brought together. For this purpose, we introduce a tagged signal model as a formal framework within which the models of computation can be precisely described and unambiguously differentiated, and their interactions can be understood. In this paper, we will focus on the interaction between dataflow models, which have partially ordered events, and discrete-event models, with their notion of time that usually defines a total order of events. A variety of interaction semantics, mainly in handling the different notions of time in the two models, are explored to illustrate the subtleties involved. An implementation based on the Ptolemy system from U.C. Berkeley is described and critiqued.

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MODELING METHODOLOGY FOR PERFORMANCE EVALUATION OF PARALLEL ARCHITECTURES A CASE STUDY, LCAP

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International Journal of High Speed Computing 1989年第4期1卷 563-601页

作者： J.P. PROST M. BECKER Post-Doc. Scientific Visitor IBM Corp. Data Systems Division Dept. 48B/MS 428 Neighborhood Rd Kingston NY 12401 USA Head of Computer Science Dept: Institut National des Télécommunications Les Epinettes 9 Rue Charles Fourier 91011 Evry Cedex France

This paper presents a modeling methodology devoted to the performance evaluation of parallel architectures. The methodology is based on the decomposition of the modeling process into seven stages. In each stage specific techniques, appropriate to parallel architectures, are applied, such as aggregation methods, a thorough distinction between the architecture model and the application program model, the constitution of program classes using data analysis techniques. The methodology is then illustrated through a case study, the loosely Coupled Array of Processors (lCAP) system, designed at IBM Kingston. Use of the lCAP model allows to predict the performance of the lCAP system, in terms of response time, resource utilization, waiting times, and to investigate many alternatives with regard to the system configuration (e. g. number of system components, component interconnection scheme, component characteristics), or to the parallel program structure (e. g. parallel task granularity, load imbalance).

关键词： loosely Coupled Array of Processors modeling methodology parallel architectures performance evaluation queueing network simulation

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A simulation model of a picture archival and communication system

A simulation model of a picture archival and communication s...

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Medical Imaging II 1988

作者： D'Silva, Vijay Perros, Harry Stockbridge, Chris Networks and Communications Digital Equipment Corporation LittletonMA01460 United States Computer Science Dept. North Carolina State University RaleighNC27695 United States Mechanical Engineering Dept. Prairie View University Prairie ViewTX77446 United States

A PACS architecture was simulated to quantify its performance. The model consisted of reading stations, acquisition nodes, communication links, a database management system, and a storage system consisting of magnetic and optical disks. Two levels of storage were simulated, a high-speed magnetic disk system for short term storage, and optical disk jukeboxes for long term storage. The communications link was a single bus via which image data were requested and delivered. Real input data to the simulation model were obtained from surveys of radiology procedures (Bowman Gray School of Medicine). From these the following inputs were calculated: - the size of short term storage necessary - the amount of long term storage required - the frequency of access of each store, and - the distribution of the number of films requested per diagnosis. The performance measures obtained were - the mean retrieval time for an image, - mean queue lengths, and - the utilization of each device. Parametric analysis was done for - the bus speed, - the packet size for the communications link, - the record size on the magnetic disk, - compression ratio, - influx of new images, - DBMS time, and - diagnosis think times. Plots give the optimum values for those values of input speed and device performance which are sufficient to achieve subsecond image retrieval times. © 1988 SPIE. All rights reserved.

关键词： database systems

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A computer architecture for large (Distributed) data bases 1

A computer architecture for large (Distributed) data bases

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1st International Conference on Very Large data Bases, VLDB 1975

作者： Peebles, Richard Manning, Eric Computer Communications Networks Group Dept. of Computer Science University of Waterloo Canada

ISBN: (纸本)9781450339209

It is argued that the data-base of a nation-wide organization will exhibit geographic locality of reference. That is, most of the transactions homing on a given component of the data base originate from a particular geographic region. At the same time there is a need to operate the collection of components as a single data base to provide for occasional transactions which cross regional boundaries, and for managerial queries and retrieval operations that span the entire data base. There are several examples of this associated with business and industry: credit and inventory records for example. Modest CPU power will suffice to perform most transaction processing on the data base. We are therefore led to consider a network of identical mini computers (or midis). Each host will execute an identical copy of the operating system in the network. The machines differ only= their complement of hardware (number of discs, primary storage size, etc.) and in the data they hold. Hence we assume that we are able to specify host hardware, host software and communications subnetwork as a single integrated system. The major goal of this work has been to investigate how far these freedoms can be exploited to yield simple elegant structures. The paper summarizes the design of the communication nucleus (4) of the network and focusses primarily on the design of the software to support transaction processing against the data base (3). Processor distribution is extended to include the ideas of a terminal host, a disc host, a central host and a communications device. The application of the proposed architecture to a typical commercial data processing problem is outlined.

关键词： computer architecture

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Advances in Robotics 1

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丛书名： Lecture Notes in computer Science

1000年

作者： Jong-Hwan Kim Shuzhi Sam Ge Prahlad Vadakkepat Abdullah Al Manum Norbert Jesse Sadasivan Puthusserypady K Ulrich Rückert Joaquin Sitte Ulf Witkowski Ryohei Nakatsu Jacky Baltes John Anderson Igor Verner

ISBN: (数字)9783642039836

ISBN: (纸本)9783642039829

th This volume is an edition of the papers selected from the 12 FIRA RoboWorld C- gress, held in Incheon, Korea, August 16–18, 2009. The Federation of International Robosoccer Association (FIRA – www. fira. net) is a non-profit organization, which organizes robotic competitions and meetings around the globe annually. The RoboSoccer competitions started in 1996 and FIRA was - tablished on June 5, 1997. The Robot Soccer competitions are aimed at promoting the spirit of science and technology to the younger generation. The congress is a forum in which to share ideas and future directions of technologies, and to enlarge the human networks in robotics area. The objectives of the FIRA Cup and Congress are to explore the technical dev- opment and achievement in the field of robotics, and provide participants with a robot festival including technical presentations, robot soccer competitions and exhibits - der the theme “Where Theory and Practice Meet. ” th Under the umbrella of the 12 FIRA RoboWorld Congress Incheon 2009, six int- national conferences were held for greater impact and scientific exchange: th • 6 International Conference on Computational Intelligence, Robotics and Autonomous Systems (CIRAS) th • 5 International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE) • International Conference on Social Robotics (ICSR) • International Conference on Advanced Humanoid Robotics Research (ICAHRR) • International Conference on Entertainment Robotics (ICER) • International Robotics Education Forum (IREF) This volume consists of selected quality papers from the six conferences.

关键词： Artificial Intelligence User Interfaces and Human computer Interaction computers and Society computers and Education Personal Computing computer Appl. in Social and Behavioral Sciences

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Applications of Evolutionary Computing 1

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丛书名： Lecture Notes in computer Science

1000年

作者： Stefano Cagnoni Colin G. Johnson Juan J. Romero Cardalda Elena Marchiori David W. Corne Jean-Arcady Meyer Agnès Guillot Jens Gottlieb Martin Middendorf Günther R. Raidl Emma Hart

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