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25th International Joint Conference on Artificial Intelligence, IJCAI 2016

作者： Pan, Shirui Wu, Jia Zhu, Xingquan Zhang, Chengqi Wang, Yang Centre for Quantum Computation and Intelligent System FEIT University of Technology Sydney Australia Dept. of Computer and Electrical Engineering and Computer Science Florida Atlantic University United States University of New South Wales Australia

Information network mining often requires examination of linkage relationships between nodes for analysis. Recently, network representation has emerged to represent each node in a vector format, embedding network structure, so off-the-shelf machine learning methods can be directly applied for analysis. To date, existing methods only focus on one aspect of node information and cannot leverage node labels. In this paper, we propose TriDNR, a tri-party deep network representation model, using information from three parties: node structure, node content, and node labels (if available) to jointly learn optimal node representation. TriDNR is based on our new coupled deep natural language module, whose learning is enforced at three levels: (1) at the network structure level, TriDNR exploits inter-node relationship by maximizing the probability of observing surrounding nodes given a node in random walks;(2) at the node content level, TriDNR captures node-word correlation by maximizing the co-occurrence of word sequence given a node;and (3) at the node label level, TriDNR models label-word correspondence by maximizing the probability of word sequence given a class label. The tri-party information is jointly fed into the neural network model to mutually enhance each other to learn optimal representation, and results in up to 79% classification accuracy gain, compared to state-of-the-art methods.

关键词： Classification (of information)

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25th Annual computational Neuroscience Meeting CNS-2016, Seogwipo City, South Korea, July 2-7, 2016 Abstracts

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BMC NEUROSCIENCE 2016年第1期17卷 1-112页

作者： [Anonymous] Computational Neurobiology Laboratory The Salk Institute for Biological Studies San Diego USA UNIC CNRS Gif sur Yvette France The European Institute for Theoretical Neuroscience (EITN) Paris France ATR Computational Neuroscience Laboratories Kyoto Japan Krembil Research Institute University Health Network Toronto Canada Department of Physiology University of Toronto Toronto Canada Department of Medicine (Neurology) University of Toronto Toronto Canada Department of Physics University of New Hampshire Durham USA Department of Neurophysiology Nencki Institute of Experimental Biology Warsaw Poland Department of Theory Wigner Research Centre for Physics of the Hungarian Academy of Sciences Budapest Hungary Department of Mathematical Sciences KAIST Daejoen Republic of Korea Department of Mathematics University of Houston Houston USA Department of Biochemistry & Cell Biology and Institute of Biosciences and Bioengineering Rice University Houston USA Department of Biology and Biochemistry University of Houston Houston USA Grupo de Neurocomputación Biológica Dpto. de Ingeniería Informática Escuela Politécnica Superior Universidad Autónoma de Madrid Madrid Spain Department of Biological Sciences University of Southern California Los Angeles USA Center for Neuroscience Korea Institute of Science and Technology Seoul South Korea Department of Neurology Albert Einstein College of Medicine Bronx USA Center for Neuroscience KIST Seoul South Korea Department of Neuroscience University of Science and Technology Daejon South Korea Systems Neuroscience Group QIMR Berghofer Medical Research Institute Herston Australia Department of Psychology Yonsei University Seoul South Korea Department of Psychiatry Kyung Hee University Hospital at Gangdong Seoul South Korea Department of Psychiatry Veterans Administration Boston Healthcare System and Harvard Medical School Brockton USA Department of Electrical and Electronic Engineering The University of Melbourne Parkvil

A1 Functional advantages of cell-type heterogeneity in neural circuits Tatyana O. Sharpee A2 Mesoscopic modeling of propagating waves in visual cortex Alain Destexhe A3 Dynamics and biomarkers of mental disorders Mitsuo Kawato F1 Precise recruitment of spiking output at theta frequencies requires dendritic h-channels in multi-compartment models of oriens-lacunosum/moleculare hippocampal interneurons Vladislav Sekulić, Frances K. Skinner F2 Kernel methods in reconstruction of current sources from extracellular potentials for single cells and the whole brains Daniel K. Wójcik, Chaitanya Chintaluri, Dorottya Cserpán, Zoltán Somogyvári F3 The synchronized periods depend on intracellular transcriptional repression mechanisms in circadian clocks. Jae Kyoung Kim, Zachary P. Kilpatrick, Matthew R. Bennett, Kresimir Josić O1 Assessing irregularity and coordination of spiking-bursting rhythms in central pattern generators Irene Elices, David Arroyo, Rafael Levi, Francisco B. Rodriguez, Pablo Varona O2 Regulation of top-down processing by cortically-projecting parvalbumin positive neurons in basal forebrain Eunjin Hwang, Bowon Kim, Hio-Been Han, Tae Kim, James T. McKenna, Ritchie E. Brown, Robert W. McCarley, Jee Hyun Choi O3 Modeling auditory stream segregation, build-up and bistability James Rankin, Pamela Osborn Popp, John Rinzel O4 Strong competition between tonotopic neural ensembles explains pitch-related dynamics of auditory cortex evoked fields Alejandro Tabas, André Rupp, Emili Balaguer-Ballester O5 A simple model of retinal response to multi-electrode stimulation Matias I. Maturana, David B. Grayden, Shaun L. Cloherty, Tatiana Kameneva, Michael R. Ibbotson, Hamish Meffin O6 Noise correlations in V4 area correlate with behavioral performance in visual discrimination task Veronika Koren, Timm Lochmann, Valentin Dragoi, Klaus Obermayer O7 Input-location dependent gain modulation in cerebellar nucleus neurons Maria Psarrou, Maria Schilstra, Neil Davey, Benjamin Torben-Ni

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Efficient mapping of an image processing application for a network-on-chip based implementation

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International Journal of High Performance systems Architecture 2009年第1期2卷 46-57页

作者： Da Silva, Marcus Vinícius Carvalho Nedjah, Nadia De Macedo Mourelle, Luiza Dept. of Electronics Engineering and Telecommunications State University of Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20550-900 Rio de Janeiro Brazil Dept. of Systems Engineering and Computation State University of Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20550-900 Rio de Janeiro Brazil Electronics Engineering Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Department of System Engineering and Computation Faculty of Engineering State University of Rio de Janeiro Brazil

Network-on-chip (NoC) is considered the next generation of communication infrastructure, which will be omnipresent in different environments. In the platform-based methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. Increasing scale integration increases the number of possible IPs to be addressed on a NoC platform. In this paper, we propose a multi-objective evolutionary-based mapping of an image processing application on a NoC based platform. The IP mapping is driven by the area occupied, execution time and power consumption. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Mapping

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Efficient hardware for modular exponentiation using the sliding-window method

Efficient hardware for modular exponentiation using the slid...

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4th International Conference on Information Technology-New Generations, ITNG 2007

作者： Nedjah, Nadia De Macedo Mourelle, Luiza Da Silva, Rodrigo Martins Dept. of Electronics Engineering and Telecommunications State University of Rio de Janeiro Brazil Dept. of System Engineering and Computation State University of Rio de Janeiro Brazil

ISBN: (纸本)0769527760

Modular exponentiation is an essential operations for various applications, such as cryptography. The performance of this operations has a tremendous impact on the efficiency of the whole application. Therefore, many researchers devoted special interest to providing smart methods and efficient implementation for modular exponentaition. One these methods is the sliding-window method, which pre-processes the exponent into zero and non-zero partitions so that the number of modular multiplications required to compute the modular power is reduced. In this paper, we devise a novel harwdare for computing modular exponentiation using the sliding-window method. The implementation is efficient when compared against existing hardware implementations of the modular exponentiation. © 2007 IEEE.

关键词： Sliding mode control

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Evolutionary Resilient Substitution Boxes for Secure Cryptography Using Nash equilibrium

Evolutionary Resilient Substitution Boxes for Secure Cryptog...

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International Conference on computational Intelligence and Security

作者： Nadia Nedjah Luiza de Macedo Mourelle Dept. of Electronics Engineering Telecommunications State University of Rio de Janeiro Brazil Dept. of System Engineering Computation State University of Rio de Janeiro Brazil

ISBN: (纸本)1424406048

A substitution box (or S-box) is simply a transformation of an input sequence of bits into another. The input and output sequences do not necessarily have the same number of bits. In cryptography, S-boxes constitute a cornerstone component of symmetric key algorithms. In block ciphers, they are typically used to obscure the relationship between the plaintext and the ciphertext. Non-linear and non-correlated S-boxes are the most secure with respect to linear and differential cryptanalysis. However, such S-boxes are hard to obtain. In this paper, we focus on engineering regular S-boxes, presenting high non-linearity and low autocorrelation properties using evolutionary computation. Hence, there are three properties that need to be optimised: regularity, non-linearity and auto-correlation. We use the Nash equilibrium-based multi-objective evolutionary algorithm to engineer resilient substitution boxes

关键词： Cryptography Nash equilibrium Evolutionary computation Autocorrelation Boolean functions Resists systems engineering and theory Telecommunication computing NP-complete problem Encoding

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How many CLBs does your circuit need to be implemented?

How many CLBs does your circuit need to be implemented?

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12th IEEE International Workshop on Rapid system Prototyping

作者： Nedjah, N. De Macedo Mourelle, L. Dept. of System Eng. and Computation Engineering Faculty State University Rua Sao Francisco Xavier 524 CEP 20559-900 Rio de Janeiro RJ Brazil

A fast method to estimate the necessary area for an intended design was presented without performing deep analysis as in case of synthesis process. The number of configurable logic blocks (CLB) and the number and the size of the multiplexers combined with the flip-flops were estimated as a candidate function. The total hardware area necessary to accomodate a candidate function was determined. The total number of flip-flops required to implement the candidate function was established. An error less than 6% was observed when the estimation method was compared with synthesis tool.

关键词： VLSI circuits

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