A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to sui...
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ISBN:
(纸本)1424400384
A reconfigurable cache architecture for object-oriented application-specific instruction set processors (ASIP) is presented in this paper. The embedded ASIPs we follow in this research are specifically designed to suit object-oriented applications and are synthesized form an object-oriented highlevel specification. The ASIPs are composed of a processor core along with a number of hardware functional units. In order to support concurrent execution of the functional units, we propose a cache architecture which is virtually divided into a number of partitions. The partition sizes can be dynamically changed depending on the run-time behavior of the application. Partitioning the cache not only provides the concurrent memory access for the functional units, but also reduces the number of tag comparisons per cache access. We also develop a simple and energy-efficient cache consistency mechanism among cache partitions. In this paper we evaluate the impact of the proposed cache architecture on the cache energy consumption, by implementing it in a number of our ASIPs. The results show that the proposed cache architecture reduces the number of tag comparisons per cache access by 39% on average.
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Forecasting Irradiance value well ahead may allow a Power system Engineer to decide the generating capacity of a thermal power plant to achieve Economic Load Dispatch (ELD) and indirectly this may reduce the usage of ...
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A fully coupled Electro-Thermo-Mechanical model is proposed in which the governing equations are derived within a continuum mechanics framework. This 1-D model is able to take into account shape memory effect and the ...
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