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Comparative Analysis of a Proposed Low-Power Adiabatic NOR Gate 26

Comparative Analysis of a Proposed Low-Power Adiabatic NOR G...

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26th International Conference on Computer and Information technology, ICCIT 2023

作者： Ganguly, Chamak Meem, Mazeda Zafor Abdullah Faruque, Mohammed Kifayat Kabir, S.M. Hossen Rakib, Saeed Arefin, Khandaker Shams Primeasia University Dept. of EEE Dhaka Bangladesh Ahsanullah University of Science and Technology Dept. of EEE Dhaka Bangladesh ULKASEMI Pvt. Limited Circuit and System Design Dhaka Bangladesh Neural Semiconductor Limited Physical Design Dhaka Bangladesh

ISBN: (纸本)9798350359015

This paper discusses the low-power adiabatic models because the power and energy consumption increase of our used devices has become significant. In this thought, the solution of using the battery has become complex as a scale-down battery means a low power supply has to be given, and the threshold voltage of the transistors has to decrease. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) come forward to mitigate the high-power consumption, which results in thinner gate-oxide, gate leakage, and power dissipation. The adiabatic technique is also one of the methods for reducing power in a device where a pulsating AC voltage is used instead of a constant voltage supply. This study proposes an adiabatic circuit for a NOR gate using a 32nm LP PTM Model. The comparative study, among the proposed circuit and PFAL, IPFAL, 2n2n2p, and ECRL used industry-standard software Cadence and LTSpice. Results show outstanding performance in power and energy dissipation as well as lower propagation delay in terms of the proposed inverter circuit, which is approximately 5.61% less than the adiabatic circuit 2N2N2P at 100MHz which has the lowest propagation delay other than the proposed inverter circuit. Power dissipation is reduced up to 77% in the proposed inverter circuit compared to the 2N2N2P adiabatic inverter circuit, which provides lower power among all the adiabatic circuits used in the experiment at 25MHz frequency. Similarly, the power dissipation for the proposed NOR circuit becomes 93% less than ECRL, which shows the lowest results after the proposed circuit at 25MHz frequency. © 2023 IEEE.

关键词： Adiabatic IPFAL (Improved Positive Feedback Adiabatic Logic) ECRL (Efficient energy recovery logic) Low-power NOR gate PFAL (Positive Feedback Adiabatic Logic) VLSI

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Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic 26

Analysis of a Low-Power Full Adder and Half Adder Using a Ne...

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26th International Conference on Computer and Information technology, ICCIT 2023

作者： Ganguly, Chamak Meem, Mazeda Zafor Kifayat Kabir, S.M. Biswas, Satyendra N. Primeasia University Dept. of EEE Dhaka Bangladesh Ahsanullah University of Science and Technology Dept. of EEE Dhaka Bangladesh ULKASEMI Pvt. Limited Circuit and System Design Dhaka Bangladesh Bloomsburg University Dept.of EEE AUST Dhaka Bangladesh and Dept. of BiCEP PA17815 United States

ISBN: (纸本)9798350359015

In today's fast-paced technological era, electronic devices must be both speedy and energy-efficient to keep up with rapid advancements. Developing energy-efficient digital devices for real-time applications is critical in VLSI research. The adiabatic process of logic circuits is used to develop an adder with high performance and ultra-low power dissipation. Techniques like multi-threshold devices (MTCMOS), variable multi-threshold devices (VTCMOS), and dynamic threshold devices (DTCMOS) have been explored with the scaling of devices. The proposed circuit contains a new type of adiabatic circuit that works excellently for low-power dissipation. A comparison is made with the conventional CMOS adders, such as half and full adders and newly developed adiabatic logic circuits. All the experimental simulations have been carried out using LTSpice software for 16nm and 22nm LP PTM models by changing frequencies from 0MHz to 25MHz, taking rise and fall time as 1n & 2n seconds respectively. We have also varied the load capacitance from 0f to 10f. The outcomes obtained from the experiment indicate the effectiveness and capability of the newly proposed circuit, which is 40% less power consumption and 22% less energy consumption for both 16nm and 22nm, respectively, using 0f as load capacitance. © 2023 IEEE.

关键词： Adiabatic CMOS Full adder Half adder Low power circuit power dissipation VLSI

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Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic

Analysis of a Low-Power Full Adder and Half Adder Using a Ne...

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International Conference on Computer and Information technology (ICCIT)

作者： Chamak Ganguly Mazeda Zafor Meem S.M Kifayat Kabir Satyendra N. Biswas Dept. of EEE Primeasia University Dhaka Bangladesh Dept. of EEE Ahsanullah University of Science and Technology Dhaka Bangladesh Circuit and System Design ULKASEMI Pvt. Limited Dhaka Bangladesh Dept.of EEE AUST Dhaka Bangladesh and Dept. of BiCEP Bloomsburg University PA USA

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Comparative Analysis of a Proposed Low-Power Adiabatic NOR Gate

Comparative Analysis of a Proposed Low-Power Adiabatic NOR G...

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International Conference on Computer and Information technology (ICCIT)

作者： Chamak Ganguly Mazeda Zafor Meem Mohammed Abdullah Faruque S. M Kifayat Kabir Saeed Hossen Rakib Khandaker Shams Arefin Dept. of EEE Primeasia University Dhaka Bangladesh Dept. of EEE Ahsanullah University of Science and Technology Dhaka Bangladesh Circuit and System Design ULKASEMI Pvt. Limited Dhaka Bangladesh Physical Design Neural Semiconductor Limited Dhaka Bangladesh

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Performance Analysis of a New Low Power BIST Technique in VLSI circuit by Reducing the Input Vectors 6

Performance Analysis of a New Low Power BIST Technique in VL...

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6th International Conference on Electrical Information and Communication technology, EICT 2023

作者： Kifayat Kabir, S.M. Motalib, Raihan Javed, Fakrul Islam Ganguly, Chamak Rakib, Saeed Hossen Biswas, Satyendra N. ULKASEMI Pvt. Limited Circuit and System Design Dhaka Bangladesh ULKASEMI Pvt. Limited IC Physical Design Dhaka Bangladesh Ltd. ASIC Physical Design Dhaka Bangladesh Primeasia University Electrical and Electronic Engineering Dhaka Bangladesh Neural Semiconductor Ltd Physical Design Dhaka Bangladesh Bloomsburg University Dept. of BiCEP PA17815 United States Ahsanullah University of Science and Technology Electrical and Electronic Engineering Dhaka Bangladesh

ISBN: (纸本)9798350370836

VLSI circuit testing is complex and costs over 30% of the total IC design. The built-in self-testing technique is popular for its extensive fault coverage and efficiency. BIST refers to a hardware device testing construction used to perform fault detection and improve the device's performance to ensure a fault- free environment to avoid causing damage within the device's lifetime. As ICs are getting more complex day by day, different BIST modules are needed to test different circuits, which increase complication in design. As a result, power consumption and clock cycle increase. This research introduces a new Built-in Self-Test (BIST) technique for VLSI circuits. To deal with the shortcomings of conventional techniques, a BIST technique is proposed, which can test the circuit's functionality and detect faults successfully. The proposed model has been implemented using 22nm PTM model by employing LTSpice simulation software. The proposed model decreases power consumption upto 47.54% in without fault, 45.34% in open circuit fault and 45.63% in short circuit fault conditions compared to conventional technique and reduces the input vectors which in turn minimizes design intricacy and ensures an improved and novel approach for self-testing compared to many other existing BIST techniques. © 2023 IEEE.

关键词： Fault detection

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Sensitivity Analysis of a Low-Power Wake-Up Receiver Using an RF Barker Code SAW Correlator and a Baseband Narrowband Correlator

Sensitivity Analysis of a Low-Power Wake-Up Receiver Using a...

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IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)

作者： Saed Abughannam J. Christoph Scheytt Dept. of System and Circuit Technology University of Paderborn Paderborn Germany

ISBN: (数字)9781728144900

ISBN: (纸本)9781728144917

In this paper we propose a novel low-power receiver architecture which uses a direct-detection receiver in combination with a 2.44 GHz 13 bit Barker Code SAW correlator for improvement of co-channel interference. Furthermore, to improve receiver sensitivity, a narrowband baseband correlator which uses pulse position modulation (PPM) is proposed. The receiver can be used as a Wake-up Receiver (WuRx) in Wireless Sensor Networks (WSN) to minimize the power dissipation and provide asynchronous and on-demand data communication. We present a rigorous analysis of the receiver. It shows that the RF front-end (SAW correlator and envelope detector) alone suffers from poor sensitivity due to the high baseband bandwidth and the absence of an RF low noise amplifier. However, by adding the narrowband correlator with an innovative Pulse Position Modulation (PPM) scheme, the overall sensitivity of the receiver reaches -63.1 dB with an improvement of 17.7 dB due to the use of the narrowband correlator that reduces the baseband bandwidth from 50 to 0.84 MHz. By scaling the narrowband correlator bandwidth further down, the receiver sensitivity can be further improved.

关键词： Radio frequency Correlators Surface acoustic waves Receivers Baseband Envelope detectors Mathematical model

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Performance Analysis of a New Low Power BIST Technique in VLSI circuit by Reducing the Input Vectors

Performance Analysis of a New Low Power BIST Technique in VL...

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International Conference on Electrical Information and Communication technology (EICT)

作者： S. M Kifayat Kabir Raihan Motalib Fakrul Islam Javed Chamak Ganguly Saeed Hossen Rakib Satyendra N. Biswas Circuit and System Design ULKASEMI Pvt. Limited Dhaka Bangladesh IC Physical Design ULKASEMI Pvt. Limited Dhaka Bangladesh ASIC Physical Design PrimeSilicon Technology (BD) Ltd Dhaka Bangladesh Electrical and Electronic Engineering Primeasia University Dhaka Bangladesh Physical Design Neural Semiconductor Ltd Dhaka Bangladesh Dept. of BiCEP Bloomsburg University PA USA Electrical and Electronic Engineering Ahsanullah University of Science and Technology Dhaka Bangladesh

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Design of an automotive visible light communications link using an off-the-shelf LED headlight 16

Design of an automotive visible light communications link us...

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16. GMM/ITG-Fachtagung ANALOG 2018: Meet Your CAD Guy / Meet Your Designer - 16th GMM/ITG Symposium ANALOG 2018: Meet Your CAD Guy/Meet Your Designer

作者： Kruse, Stephan Kress, Christian Memedi, Agon Tebruegge, Claas Amjad, Muhammad Sohaib Scheytt, Christoph Dressler, Falko Heinz Nixdorf Institute and System and Circuit Technology Paderborn University Germany Heinz Nixdorf Institute Dept. of Computer Science Paderborn University Germany Hella GmbH and Co. KGaA Lippstadt Germany

ISBN: (纸本)9783800747542

We present a transmitter circuit to drive a commercial Light Emitting Diode (LED)-based headlight for automotive Visible Light Communication (VLC). Based on the design of the presented transmitter (TX), we provide a design methodology for VLC TXs and make it available as Open Hardware. Furthermore, a complete wireless VLC link is built using the GNU Radio signal processing tool chain and demonstrated on an Universal Software Radio Peripheral (USRP). The Total Harmonic Distortion (THD) of the system is below 5% for a wide input voltage range and the 1 dB compression point (P1dB) is at 1.02V, which makes the circuit attractive for more advanced modulation formates like Orthogonal Frequency Division Multiplexing (OFDM) or Pulse-Amplitude Modulation (PAM). © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach

关键词： Visible light communication

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Design of an Automotive Visible Light Communications Link using an Off-The-Shelf LED Headlight

Design of an Automotive Visible Light Communications Link us...

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ANALOG 2018;16th GMM/ITG-Symposium

作者： Stephan Kruse Christian Kress Agon Memedi Claas Tebruegge Muhammad Sohaib Amjad Christoph Scheytt Falko Dressler Heinz Nixdorf Institute and System and Circuit Technology Paderborn University Heinz Nixdorf Institute and Dept. of Computer Science Paderborn University

ISBN: (纸本)9783800747542

关键词： input voltage range Light emitting diodes Headlights variable length codes tool chain Telecommunication links Orthogonal frequency division multiplexing automotive engineering Total harmonic distortion Software radio off-the-shelf

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AICNN: Implementing Typical CNN Algorithms with Analog-to-Information Conversion Architecture

AICNN: Implementing Typical CNN Algorithms with Analog-to-In...

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2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017

作者： Jia, Kaige Liu, Zheyu Qiao, Fei Liu, Xinjun Wei, Qi Yang, Huazhong Tsinghua National Laboratory for Information Science and Technology Institute of Circuit and System Dept. of Electronic Engineering Tsinghua University China Dept. of Mechanical Engineering Tsinghua University China

ISBN: (纸本)9781509067626

AICNN architecture is presented in this work to map the state-of-the-art machine-learning algorithms of CNN to power-constrained embedded hardware. As the combination of analog-to-information conversion and typical CNN algorithms, AICNN can realize ultra-highly efficient computation by using massive parallel analog signal processing circuits, which could also significantly reduce ADC devices cost of converting sensors' outputs. As a design example, the specific AICNN-3 implementation is evaluated, which realize the minimum system of typical CNN task using AICNN architecture, with SMIC 0.18 μm CMOS process. Simulation results show that the AICNN-3 can classify a 28x28 MNIST image with only 1.47nJ. Compared with baseline implementation on CPU, the AICNN-3 could achieve 67000x energy-efficiency improvement, however the accuracy loss is less than 1%. Moreover, the influences of devices mismatch and process variations are evaluated using Monte Carlo statistical method, for the imperfection of analog processing paradigm, as well as the scalability of AICNN architecture is also discussed. © 2017 IEEE.

关键词： Energy efficiency

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