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URSI Atlantic Radio Science Meeting

作者： Saed Abughannam J. Christoph Scheytt Dept. of System and Circuit Technology Heinz Nixdorf Institute University of Paderbom Paderborn Germany

ISBN: (纸本)9781538637647

This paper demonstrates system level analysis of an energy efficient Radio Frequency (RF) receiver. The receiver is based on a Surface Acoustic Wave (SAW) correlator which is used for highly linear demodulation and interferer suppression in conjunction with envelope detection for ultra-low power dissipation and hardware efficiency. The receiver is to be used in Wireless Sensor Networks (WSN) as a Wake-up Receiver (WuR) to reduce the network nodes power dissipation and provide asynchronous data communication. Low latency and high interference robustness makes this scheme interesting for industrial real-time applications. In this paper, the SAW correlator transfer function is derived, which functions as a Matched Filter (MF). Since the receiver uses envelope detection and based on the characteristic of the SAW, the receiver sensitivity is analyzed by means of a non-linear approach.

关键词： receiver SAW WSN

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An Ultra-fast and Low-power Design of Analog circuit Network for DoG Pyramid Construction of SIFT Algorithm

An Ultra-fast and Low-power Design of Analog Circuit Network...

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International Symposium on Quality Electronic Design

作者： Zheyu Liu Fei Qiao Qi Wei Xinghua Yang Yi Li Huazhong Yang Tsinghua National Laboratory for Information Science and Technology Institute of Circuit and System Dept. of Electronic Engineering Tsinghua University

ISBN: (纸本)9781509012145

SIFT algorithm is the most popular and widely used computer vision method for image feature extraction, because of its excellent robustness for various transformations, while the computational burden and huge hardware requirements limit the applications of SIFT algorithm, especially for the real-time and energy-efficient embedded machine vision systems. In this paper, a hardware accelerator of analog circuit network for the Gaussian scale space establishment has been proposed, which is the most computationally expensive of SIFT algorithm. The accelerator adopts a current-mode circuit network operating in sub-threshold region, so that the power dissipation can be very low. Moreover, extensive repetitive multiplication and addition operations are completed in analog domain directly, before the original data is transformed to digital domain by ADC. Thus, the calculation time is approximately equal to the settling time of circuit network, which is usually down to several nano-seconds. Simulations with standard CMOS process have demonstrated that the processing speed is about 400 ps/pixel, while the power consumption is only 1.8 mW. The overall processing speed for VGA-format (640*480) image is up to 600 fps, which is at least 27X faster than the state-of-art digital counterparts systems.

关键词： SIFT Gaussian convolution Analog circuit network Real-time Sub-threshold

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Physical Computing circuit With No Clock to Establish Gaussian Pyramid of SIFT Algorithm

Physical Computing Circuit With No Clock to Establish Gaussi...

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IEEE International Symposium on circuits and systems

作者： Yi Li Fei Qiao Qi Wei Huazhong Yang Institute of Circuit and System Dept. of Electronic Engineering Tsinghua University Tsinghua National Laboratory for Information Science and Technology

ISBN: (纸本)9781479983926

Physical computing scheme of active resistor network is proposed in this paper to set up a multi-scale Gaussian filter, which is also called Gaussian Pyramid in image signal processing. The analog output signal of each image photodiode could be directly processed by the circuit topology of an active resistor network, which has been pre-designed to meet the requirement of the complicated Gaussian Pyramid in SIFT algorithm. Since it is operated with no clock, the physical computing scheme, with only setup time of the whole processing circuits, is much faster than various current digital realizations. The circuit-level simulation with 65nm CMOS technology has been carried out, which shows the energy consumption of the Gaussian Pyramid processing circuit is around 74.79pJ to filter a frame of 256 × 256 pixel image, and the circuit setting time of the processing is about 138.03ps, considering the parasitic capacitances of each nodes of the circuits. Furthermore, the presented circuit is integrated into a smart CMOS image sensor architecture. With the same processing procedure, the new method of active resistor network could achieve 1.58× speedup when compared with its counterpart of FPGA implementation, in which the column-parallel readout technology of analog-to-digital convertor is used.

关键词： Resistance Networks circuit topology Gauss image signal Parasitic capacitance Speeding energy consumption Timing devices outgoing signal setting time PIXEL IMAGE

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Analyses of piezoresistive and mechanical characteristics of nano polysilicon film

Analyses of piezoresistive and mechanical characteristics of...

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International Conference on Software Intelligence Technologies and Applications and International Conference on Frontiers of Internet of Things, 2014

作者： Lu, Xuebin Cui, Linhai Huang, Hai Dept. of Integrate Circuit Design and Integrate System Harbin University of Science and Technology China

ISBN: (纸本)9781849199704

In order to take good advantage of nano polysilicon film, piezoresistive and mechanical characteristics of the nano polysilicon film are very necessary to investigated. In this paper, the nano polysilicon films were prepared by low pressure chemical vapour deposition under different technical parameters, including thickness, deposition temperature and doping concentration, which are very important for preparation of the nanofilm. The experimental results of piezoresistive and temperature characteristics show that the optimized technical parameters are followed, the thickness is about 90nm, the deposition temperature is 620, and the doping concentration is about 4.1×1019cm-3 or between 2.0×1020cm-3 and 4.1×1020cm-3 from different point of view. The experimental results of Young's modulus show that the mechanical characteristic of nano polysilicon film is almost independent of thickness. The piezoresistive performance of nano polysilicon film is better than that of single silicon under same doping concentration. The investigation of piezoresistive and mechanical characteristics of the nano polysilicon film is very useful for application of piezoresistive sensor, which can be used in the internet of things.

关键词： Elastic moduli

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Analyses of piezoresistive and mechanical characteristics of nano polysilicon film

Analyses of piezoresistive and mechanical characteristics of...

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International Conference on Software Intelligence Technologies and Applications & International Conference on Frontiers of Internet of Things 2014

作者： Xuebin Lu Linhai Cui Hai Huang Dept. of Integrate Circuit Design and Integrate System Harbin University of Science and Technology China

In order to take good advantage of nano polysilicon film, piezoresistive and mechanical characteristics of the nano polysilicon film are very necessary to investigated. In this paper, the nano polysilicon films were prepared by low pressure chemical vapour deposition under different technical parameters, including thickness, deposition temperature and doping concentration, which are very important for preparation of the nanofilm. The experimental results of piezoresistive and temperature characteristics show that the optimized technical parameters are followed, the thickness is about 90nm, the deposition temperature is 620°C, and the doping concentration is about 4.1×10 19 cm -3 or between 2.0×10 20 cm -3 and 4.1×10 20 cm -3 from different point of view. The experimental results of Young's modulus show that the mechanical characteristic of nano polysilicon film is almost independent of thickness. The piezoresistive performance of nano polysilicon film is better than that of single silicon under same doping concentration. The investigation of piezoresistive and mechanical characteristics of the nano polysilicon film is very useful for application of piezoresistive sensor, which can be used in the internet of things.

关键词： Piezoresistive Sensor Piezoresistive performance Technical Parameters Young's Modulus piezoresistance technological parameter Elastic Modulus Mechanical properties Polysilicon Low pressure chemical vapor deposition Nanotechnologies Films

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A digital framework for pulse coded neural network hardware with bit-serial operation

A digital framework for pulse coded neural network hardware ...

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7th International Conference on Hybrid Intelligent systems, HIS 2007

作者： Kaulmann, Tim Dikmen, Deniz Rückert, Ulrich Heinz Nixdorf Institute University of Paderborn Dept. of System and Circuit Technology Fuerstenallee 11 33102 Paderborn Germany

ISBN: (纸本)0769529461

This publication presents a digital framework for building up pulse coded neural networks with leaky integrate-and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication infrastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bitserial operation has been verified by simulations. © 2007 IEEE.

关键词： Network coding

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Fault injection system for automatic testing system

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Journal of Harbin Institute of technology(New Series) 2003年第3期10卷 321-324页

作者：王胜文洪炳熔 Dept. of Computer Science and Engineering Harbin Institute of Technology Harbin 150001 China Dept. of Computer Science and Engineering Harbin Institute of Technology Harbin 150001 Chinaonsidering the deficiency of the means for confirming the attribution of fault redundancy in the research of Automatic Testing System(ATS) a fault-injection system has been proposed to study fault redundancy of automatic testing system through compurison. By means of a fault-imbeded environmental simulation the faults injected at the input level of the software are under test. These faults may induce inherent failure mode thus bringing about unexpected output and the anticipated goal of the test is attained. The fault injection consists of voltage signal generator current signal generator and rear drive circuit which are specially developed and the ATS can work regularly by means of software simulation. The experimental results indicate that the fault injection system can find the deficiency of the automatic testing software and identify the preference of fault redundancy. On the other hand some soft deficiency never exposed before can be identified by analyzing the testing results.

Considering the deficiency of the means for confirming the attribution of fault redundancy in the re-search of Automatic Testing system(ATS) , a fault-injection system has been proposed to study fault redundancyof automatic testing system through compurison. By means of a fault-imbeded environmental simulation, thefaults injected at the input level of the software are under test. These faults may induce inherent failure mode,thus bringing about unexpected output, and the anticipated goal of the test is attained. The fault injection con-sists of voltage signal generator, current signal generator and rear drive circuit which are specially developed,and the ATS can work regularly by means of software simulation. The experimental results indicate that the faultinjection system can find the deficiency of the automatic testing software, and identify the preference of fault re-dundancy. On the other hand, some soft deficiency never exposed before can be identified by analyzing the tes-ting results.

关键词： Fault injection comparing method rear drive ATS

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AN ANALYSIS OF THE HOT-SPOT CONTENTION AND MESSAGE COMBINING ON THE SIMPLE SERIAL SYNCHRONIZED-MULTISTAGE INTERCONNECTION NETWORK

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systemS AND COMPUTERS IN JAPAN 1995年第9期26卷 1-12页

作者： GAYE, K HANAWA, T AMANO, H Member Faculty of Science and Technology Keio University Yokohama Japan 223 Nonmembers Tosbihiro Hanawa:received his B.E. degree in 1993 from Dept. Electrical Eng. Fac. Sci. Tech. Keio Univ. where he is presently in the Master's program. He is interested in performance analysis of interconnection network for parallel computers. Hidebaru Amano:received his B.E. and Dr. of Eng. degrees in 1981 and 1986 respectively from Keio Univ. He is engaged in research on parallelcomputer system. Presently Assoc. Prof. Dept. Electrical Eng. Fac. Sci. Tech. Keio Univ. He is co-author ofDigital Circuit for Everybody and Parallel Processing Mechanism.

Simple serial synchronized (SSS) multistage interconnection network (MIN) is a processor-memory connection network that has a high performance/cost ratio, where the packet is inputted and switch synchronously in the MIN, which has a high pass-through ratio and is composed of simple elements. This paper evaluates the effect of the hot spot contention and the effect of the synchronous bit-serial (SBS) message combining in SSS-MIN, by the theoretical analysis based on probability and simulation. In contrast to conventional MIN, there does not arise a complete tree saturation in SSS-MIN, but an area, to which the access is difficult, is produced according to the relative position to the hot spot contention. From such a viewpoint, an analysis method for the pass-through ratio is presented, which considers the position of the switching element to the hot spot. It is verified as a result of evaluation that the proposed method of analysis gives a result close to that of simulation, so long as the access to the hot spot and the connection network architecture stay within a practical range. It is also seen that the pass-through ratio is deteriorated less in SSS-MIN by the hot spot contention than in the conventional MIN, and the effect can be almost completely eliminated by the SBS message combining. When a multiprocessor system is actually constructed, performance deterioration due to hot spot contention is greater than in the case where only the pass-through ratio is considered. This can also be eliminated almost completely by the SBS message combining.

关键词： MULTISTAGE NETWORK MESSAGE COMBINING, PERFORMANCE EVALUATION MULTIPROCESSOR

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Progress in Robotics 1

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丛书名： Communications in Computer and Information Science

1000年

作者： Jong-Hwan Kim Shuzhi Sam Ge Prahlad Vadakkepat Abdullah Al Manum Ryohei Nakatsu Norbert Jesse Sadasivan Puthusserypady K Ulrich Rückert Joaquin Sitte Ulf Witkowski Thomas Braunl Jacky Baltes John Anderson Ching-Chang Wong Igor Verner David Ahlgren

ISBN: (数字)9783642039867

ISBN: (纸本)9783642039850

th This volume is an edition of the papers selected from the 12 FIRA RoboWorld C- gress, held in Incheon, Korea, August 16–18, 2009. The Federation of International Robosoccer Association (FIRA – www. fira. net) is a non-profit organization, which organizes robotic competitions and meetings around the globe annually. The RoboSoccer competitions started in 1996 and FIRA was - tablished on June 5, 1997. The Robot Soccer competitions are aimed at promoting the spirit of science and technology to the younger generation. The congress is a forum in which to share ideas and future directions of technologies, and to enlarge the human networks in robotics area. The objectives of the FIRA Cup and Congress are to explore the technical dev- opment and achievement in the field of robotics, and provide participants with a robot festival including technical presentations, robot soccer competitions and exhibits - der the theme “Where Theory and Practice Meet. ” th Under the umbrella of the 12 FIRA RoboWorld Incheon Congress 2009, six int- national conferences were held for greater impact and scientific exchange: th • 6 International Conference on Computational Intelligence, Robotics and Autonomous systems (CIRAS) th • 5 International Symposium on Autonomous Minirobots for Research and Edutainment (AMiRE) • International Conference on Social Robotics (ICSR) • International Conference on Advanced Humanoid Robotics Research (ICAHRR) • International Conference on Entertainment Robotics (ICER) • International Robotics Education Forum (IREF) This volume consists of selected quality papers from the six conferences.

关键词： Robotics and Automation Artificial Intelligence User Interfaces and Human Computer Interaction Computers and Society Computers and Education Personal Computing

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