Recently, the interest in biophilic design and indoor greenery has been increasing. However, the growth of indoor plants may become stunted owing to unfavorable light conditions. Therefore, a method for evaluating the...
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In recent years, interest in biophilic design and indoor greenery has increased. However, the growth of indoor plants may become stunted under unfavorable light conditions. Therefore, we must evaluate the light enviro...
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In recent years, interest in biophilic design and indoor greenery has increased. However, the growth of indoor plants may become stunted under unfavorable light conditions. Therefore, we must evaluate the light environments required for indoor plants to thrive. We propose a new method to assess indoor light environments for indoor plants by using spectral irradiance simulation. We verify the accuracy of the spectral irradiance simulation via actual measurements in a university classroom. Additionally, we confirm the calculation accuracy of the photosynthetic photon flux density, which is strongly correlated with photosynthesis in plants. We evaluate indoor light environments for indoor plants in 3D models by applying a few concepts from plant physiology.
This paper introduces a novel layout-style with a reasonable generation algorithm for MOS analog modules in order to guarantee complete routing and perfect matching of devices. The introduced layout-style is applicabl...
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ISBN:
(纸本)9781509061136
This paper introduces a novel layout-style with a reasonable generation algorithm for MOS analog modules in order to guarantee complete routing and perfect matching of devices. The introduced layout-style is applicable to a variety of essential MOS analog circuits. To the transistor layout, we introduce a symmetrical row-based structure where all transistors are transformed to matched pairs by duplicating sub-netlists or decomposing into sub-transistors. Further to these transistors, a generation algorithm is proposed to maximize the diffusion-sharing along the current paths. Several design examples are used to demonstrate the effectiveness of the algorithm.
We address layout generation of on-chip matched capacitors with the high relative accuracy. Our twisted common-centroid pattern of unit capacitors consider the post-placement routability as well as reduce a systematic...
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ISBN:
(纸本)9781509009169
We address layout generation of on-chip matched capacitors with the high relative accuracy. Our twisted common-centroid pattern of unit capacitors consider the post-placement routability as well as reduce a systematic mismatch induced by process gradient. We apply this algorithm to the layout design of an SAR-ADC circuit. Compared with the common spiral capacitor array, our generation method (1) produces a similar low capacitance ration mismatch, and moreover (2) a 100% routability can be achieved.
As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) techni...
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As semiconductor manufacturing processing scaling down, leakage current of CMOS circuits is becoming a dominant contributor to power dissipation. This paper provides an efficient leakage current reduction (LCR) technique for low-power and low-frequency circuit designs in terms of design rules and layout parameters related to layout dependent effects. We address the LCR technique both for analog and digital circuits, and present a design case when applying the LCR techniqe to a successive-approximation-register (SAR) analog-to-digital converter (ADC), which typically employs analog and digital transistors. In the post-layout simulation results by HSPICE, an SAR-ADC with the LCR technique achieves 38.6-nW as the total power consumption. Comparing with the design without the LCR technique, we attain about 30% total energy reduction.
This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manag...
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This paper proposes a novel design method involving the stages from analog circuit design to layout synthesis in hope of suppressing the process-induced variations with a design style called transistor array. We manage to decompose the transistors into unified sub-transistors, and arrange the sub-transistors on a uniform placement grid so that a better post-CMP profile is expected to be achieved, and that the STI-stress is evened up to alleviate the process variations. However, since lack of direct theoretical support to the transistor decomposition, we analyze and evaluate the errors arising from the decomposition in both large and small signal analysis. A test chip with decomposed transistors on it confirmed our analysis and suggested that the errors are negligibly small and the design with transistor array is applicable. Based on this conclusion, a design flow with transistor array covering from circuit design to layout synthesis is proposed, and several design cases, including three common-source amplifiers, three two-stage OPAMPS and a nano-watt current reference, are implemented on a test chip with the proposed method, to demonstrate the feasibility of our idea. The measurement results from the chip confirmed that the designs with transistor array are successful, and the proposed method is applicable.
As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synt...
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As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.
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