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Computer-Aided Logic design of Two-Level MOS Combinational Networks with Statistical Results

IEEE Transactions on Computers 1978年第10期C-27卷 911-923页

作者： El-Ziq, Yacoub M. Design Automation and Test Department SPERRY UNIVAC Roseville MN 55113 United States Department of Computer Science State University of New York at Binghamton Bing-hamton NY 13901 United States

Metal-oxide-semiconductor (MOS) logic elements offer advantages over bipolar logic elements, such as smaller size, complexity, and power consumption, as well as more flexibility and versatility. Since MOS is playing a major role in large-scale integration (LSI), synthesis of MOS networks with a large number of variables is very important. In this paper, an efficient algorithm for computer-aided synthesis of MOS combinational logic networks is presented. The algorithm can synthesize both completely and incompletely specified switching functions ofa large number ofvariables. It rapidly generates an easily testable MOS network with a near-minimum number of MOS complex cells and field-effect transistors (FET‘s). A 10-variable example is given to illustrate the algorithm step-by-step. The algorithm has been programmed in Fortran IV for SPERRY UNIVAC 1108. Many randomly generated switching functions of various numbers of variables have been executed by the computer and the required amounts of computing time and memory space are reported. Copyright © 1978 by The Institute of Electrical and Electronics Engineers. Inc.

关键词： Boolean functions combinational logic combinational networks computer algorithm diagnosable networks easily testable networks field-effect transistors logic design automation logic synthesis metal-oxide semiconductor statistical data testability

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A monolithic spectral BIST technique for control or test of analog or mixed-signal circuits

A monolithic spectral BIST technique for control or test of ...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： J.M. Emmert J.A. Cheatham Badhri Jagannathan Sandeep Umarani Microelectronic Design Automation and Test Laboratory Department of Electrical Engineering Wright State University USA

Intelligent radio frequency (RF) front ends make use of MMIC and MEMS devices to provide a limited range of programmability to what have historically been fixed resistive, capacitive, and inductive impedance matching networks. Many BIST methods for mixed-signal systems can also be used to monitor and provide feedback for the control of such RF systems. For example, spectral techniques can be used to analyze and determine the center frequency of a bandpass filter. Information relative to the center frequency can then be fed back into the system, and adjustments can be made to fine tune the filter. In this paper, we outline our spectral based, mixed-signal approach for monitoring the health of analog and RF components in mixed-signal systems on-chip. In our approach we use well known DSP techniques based an the FFT for on-chip signal generation and analysis. We reduce required hardware by using the same functional block to analyze analog output signals that we use to generate m tone stimulus signals. By providing an on-chip functional test capability, we also reduce the test time required on expensive ATE. Our techniques have been prototyped and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m process with target execution speeds of 2-16 GHz.

关键词： Circuit testing Built-in self-test Radio frequency Monitoring Band pass filters Signal generators Signal analysis Intelligent networks MMICs Microelectromechanical devices

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An FFT approximation technique suitable for on-chip generation and analysis of sinusoidal signals

An FFT approximation technique suitable for on-chip generati...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

作者： J.M. Emmert J.A. Cheatham Badhri Jagannathan Sandeep Umarani Microelectronic Design Automation and Test Lab Department of Electrical Engineering Wright State University USA

Signal generation and analysis are an important part of BIST for analog and mixed-signal systems. An accurate analysis of the spectral content of signals produced by analog components can be accomplished with a digital implementation of a fast Fourier transform (FFT) algorithm. In the past, size and speed have limited the application of such a technique to off-chip test equipment or DSP chips (primarily due to the number of multiplication operations). In this paper, we present an FFT approximation technique suitable for on-chip spectral BIST signal generation and analysis. For signal generation, we show that the noise produced by the approximation technique is under 24.74 dB for a 256 point FFT with a 32 point approximate kernel. For signal analysis, we show that the instantaneous dynamic range (IDR) for the approximation technique is under 21.80 dB for a 256 point FFT with a 32 point approximate kernel. Our techniques have been implemented and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m SiGe process for 2-16 GHz applications.

关键词： Signal generators Signal analysis Built-in self-test Kernel Spectral analysis Algorithm design and analysis Fast Fourier transforms test equipment Digital signal processing chips Noise generators

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Defect analysis and realistic fault model extensions for static random access memories

Defect analysis and realistic fault model extensions for sta...

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IEEE International Workshop on Memory Technology, design and testing

作者： K. Zarrineh A.P. Deo R.D. Adams Test Design Automation IBM Microelectronics NY USA CSE Department Suny at Buffalo Buffalo NY USA

Resistive short defects were injected in the sense amplifier, memory cells and the address decoder of an SRAM memory. The behavior of these defects were examined using a transistor-level simulation framework. An unbalanced sense amplifier fault, consisting of a resistive short injected in the pull-down path of a sense amplifier, was examined. The scope of this type of fault could be broadened to cover any type of defect that makes the right and left side of the sense amplifier to become asymmetric. The effects of resistive shorts in the pull-up and pulldown path of a memory cell were examined. For the defects in the pull-up path, the effectiveness of different test methods designed to detect this type of defects were examined. The pause method is effective for resistive defects with large values while the weak write DfT method can detect small defects by introducing structural changes to the memory cell. In the case of a defect in the pull-down path of the memory cell, two consecutive read operations were determined to be the most effective solution to detect these defects. Three types of defects were injected in the dynamic logic address decoder. The defects affecting the pulldown and the input to the N-FETs manifested themselves as the address decoder selects more than one or zero memory cell. The defects affecting the restore unit and the word address line resulted in not selecting any cell in the memory. The injected defects in the restore unit could not be detected without the addition of DfT logic to the unit.

关键词： Circuit faults Decoding Random access memory Fabrication Microelectronics Digital systems Very large scale integration Logic design Logic circuits Voltage

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Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 /spl mu/m

Architecture and implementation of an embedded reconfigurabl...

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Annual IEEE International ASIC/SOC Conference

作者： K. Leijten-Nowak A. Katoch EE Department Design Automation Group Eindhovan University of Technology Eindhoven Netherlands Digital Design and Test Group Philips Research Eindhoven Netherlands

Reconfigurable logic is gaining importance in the context of embedded systems. But cost-efficient architectures implementable in standard CMOS technology, and mature design and mapping tools for them are still missing. This paper presents a novel architecture of an embedded reconfigurable logic (RL) core optimised for DSP applications. Tuning towards the application domain allowed one to reduce the logic cell implementation cost and the logic cell routing resources by 23% and 28%, respectively, compared to a commercial FPGA device with equivalent functionality. A tile-based approach which enabled the implementation of the RL core at a reduced design effort is also described. Finally, some VLSI implementation details of the core and the test chip realised in a standard 0.13 /spl mu/m CMOS process technology are discussed.

关键词： Reconfigurable logic CMOS technology CMOS logic circuits Logic devices Embedded system Digital signal processing Cost function Routing Field programmable gate arrays Very large scale integration

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A new framework for automatic generation, insertion and verification of memory built-in self test units

A new framework for automatic generation, insertion and veri...

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VLSI test Symposium

作者： K. Zarrineh S.J. Upadhyaya Test Design Automation IBM Corporation Endicott NY USA Department of Computer Science and Engineering Suny at Buffalo Buffalo NY USA

The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.

关键词： Automatic testing Built-in self-test Logic testing Memory architecture Computer architecture Circuit testing System testing Costs Time to market design automation

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Scan chain design for test time reduction in core-based ICs

Scan chain design for test time reduction in core-based ICs

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IEEE International test Conference

作者： J. Aerts E.J. Marinissen Department of Mathematics and Computing Science Eindhovan University of Technology Eindhoven Netherlands Department of VLSI Design Automation & Test Philips Research Laboratories Eindhoven Netherlands

The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test application time and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector set for a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pins to embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number of scan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-based ICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC. Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varying design parameters.

关键词： Integrated circuit testing Automatic testing Circuit testing Pins Production Costs test equipment Logic testing Job shop scheduling Laboratories

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Power Harvesting towards Sustainable Energy Technology through Ambient Vibrations and Capacitive Transducers

Power Harvesting towards Sustainable Energy Technology throu...

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2023 International Conference on Emerging Power Technologies, ICEPT 2023

作者： Jamil, Umar Sulaiman, Muhammad Ghafoor, Nouman Malmir, Mostafa Nawaz, Faisal Shakoor, Rana I. University of Texas at San Antonio Department of Electrical Engineering San Antonio United States Air University Department of Electrical Engineering Islamabad Pakistan University of Limerick Department of Science and Engineering Limerick Ireland Ajou University Department of Electrical Engineering Suwon Korea Republic of National Center of Robotics and Automation Air University Mems Sensor Design and Test Lab Islamabad Pakistan

ISBN: (纸本)9798350301014

As part of the fourth industrial revolution, low-power electronic devices require a power harvesting system to provide energy for their operation because energy harvesting technologies are crucial for enabling 90% of wireless sensor networks. While solar and thermal energy harvesting are popular methods, they have limitations such as dependence on sunlight and thermal gradients, which make them unreliable for low-wattage electronic equipment and wireless sensing networks. Power harvesting from ambient vibrations can lead to a sustainable system. Currently, there is a focus on different power harvesting principles such as electromagnetic, piezoelectric, and electrostatic. This research work presents a novel power harvester design that uses three in-plane capacitive transducers - gap-closing, overlap-varying, and pattern-varying - to operate under ambient vibrations as input energy. With low levels of input vibrations, the device moves, leading to changes in capacitance and the harvesting of reliable electrical power. The design analysis includes capacitance, frequency, and electromechanical evaluations to acquire capacitance matrices, natural frequencies for different modes, displacement covered by moving mass, charge distribution, and pressure distribution. © 2023 IEEE.

关键词： Energy harvesting

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testing embedded-core based system chips

Testing embedded-core based system chips

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IEEE International test Conference

作者： Y. Zorian E.J. Marinissen S. Dey Logic Vision Inc. San Jose CA USA Department VLSI Design Automation & Test Philips Research Eindhoven Netherlands Department of Electrical and Computer Engineering University of California San Diego La Jolla CA USA

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. This paper provides an overview of current industrial practices as well as academic research in these areas. We also discuss industry-wide efforts by VSIA and IEEE P1500 and describe the challenges for future research.

关键词： System testing Manufacturing industries CMOS technology Circuit testing Libraries Buildings Intellectual property Manufacturing processes Assembly systems Floors

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Steady-state electron transport in the III-V nitride semiconductors: A sensitivity analysis

Steady-state electron transport in the III-V nitride semicon...

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作者： O'Leary, Stephen K. Foutz, Brian E. Shur, Michael S. Eastman, Lester F. Faculty of Engineering University of Regina Regina Sask. S4S 0A2 Canada School of Electrical Engineering Cornell University Ithaca NY 14853 United States Cadence Test Design Automation Dept V32/256-2 1701 North Street Endicott NY 13760 United States Department of Electrical Engineering Rensselaer Polytechnic Institute Troy NY 12180-3590 United States

We studied the sensitivity of the steady-state electron transport in GaN to variations in the important material parameters related to the band structure. We found (a) that an increase in the lowest conduction-band-valley effective mass leads to a lowering and broadening of the peak in the velocity-field characteristic, as well as to an increase in the field at which the peak occurs;(b) that increases in the upper conduction-band-valley effective masses dramatically decrease the saturation drift velocity, with very little other effect;(c) that increased nonparabolicity of the lowest conduction-band valley leads to a broadening and shifting to higher electric fields of the peak in the velocity-field characteristic;(d) that increases in the intervalley energy separation lead to moderate increases in the peak drift velocity;and (e) that increases in the degeneracy of the upper conduction-band valleys leads to a moderate decrease in the saturation drift velocity.

关键词： Semiconductor materials

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