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arXiv 2023年

作者： Yayla, Mikail Thomann, Simon Wei, Ming-Liang Yang, Chia-Lin Chen, Jian-Jia Amrouch, Hussam The Design Automation for Embedded Systems Group TU Dortmund University Germany Lamarr Institute for Machine Learning and Artificial Intelligence Germany Germany Germany Taiwan

Using accelerators based on analog computing is an efficient way to process the immensely large workloads in Neural Networks (NNs). One example of an analog computing scheme for NNs is Integrate-and-Fire (IF) Spiking Neural Networks (SNNs). However, to achieve high inference accuracy in IF-SNNs, the analog hardware needs to represent current-based multiply-accumulate (MAC) levels as spike times, for which a large membrane capacitor needs to be charged for a certain amount of time. A large capacitor results in high energy use, considerable area cost, and long latency, constituting one of the major bottlenecks in analog IF-SNN implementations. In this work, we propose a HW/SW Codesign method, called CapMin, for capacitor size minimization in analog computing IF-SNNs. CapMin minimizes the capacitor size by reducing the number of spike times needed for accurate operation of the HW, based on the absolute frequency of MAC level occurrences in the SW. To increase the operation of IF-SNNs to current variation, we propose the method CapMin-V, which trades capacitor size for protection based on the reduced capacitor size found in CapMin. In our experiments, CapMin achieves more than a 14× reduction in capacitor size over the state of the art, while CapMin-V achieves increased variation tolerance in the IF-SNN operation, requiring only a small increase in capacitor size. Copyright © 2023, The Authors. All rights reserved.

关键词： Neural networks

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Renovation of edgecloudsim: An efficient discrete-event approach

arXiv

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arXiv 2021年

作者： Freymann, Raphael Shi, Junjie Chen, Jian-Jia Chen, Kuan-Hsun Design Automation for Embedded Systems Group Department of Informatics TU Dortmund University Germany

Due to the growing popularity of the Internet of Things, edge computing concept has been widely studied to relieve the load on the original cloud and networks while improving the service quality for end-users. To simulate such a complex environment involving edge and cloud computing, EdgeCloudSim has been widely adopted. However, it suffers from certain efficiency and scalability issues due to the ignorance of the deficiency in the originally adopted data structures and maintenance strategies. Specifically, it generates all events at beginning of the simulation and stores unnecessary historical information, both result in unnecessarily high complexity for search operations. In this work, by fixing the mismatches on the concept of discrete-event simulation, we propose enhancement of EdgeCloudSim which improves not only the runtime efficiency of simulation, but also the flexibility and scalability. Through extensive experiments with statistical methods, we show that the enhancement does not affect the expressiveness of simulations while obtaining 2 orders of magnitude speedup, especially when the device count is large. Copyright © 2021, The Authors. All rights reserved.

关键词： Edge computing

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Demo Abstract: Perception vs. Reality - Never Believe in What You See

Demo Abstract: Perception vs. Reality - Never Believe in Wha...

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International Symposium on Information Processing in Sensor Networks (IPSN)

作者： Yunfeng Huang Fang-Jing Wu Christian Hakert Georg von der Brüggen Kuan-Hsun Chen Jian-Jia Chen Patrick Böcker Petr Chernikov Luis Cruz Zeyi Duan Ahmed Gheith Yantao Gong Anand Gopalan Karthik Prakash Ammar Tauqir Yue Wang Communication Network Institute & Design Automation for Embedded Systems Group Dortmund

ISBN: (数字)9781728154978

ISBN: (纸本)9781728154985

The increasing availability of heterogeneous ambient sensing systems challenges the according information processing systems to analyse and compare a variety of different systems in a single scenario. For instance, localization of objects can be performed by image processing systems as well as by radio based localization. If such systems are utilized to localize the same objects, synergy of the outputs is important to enable comparable and meaningful analysis. This demo showcases the practical deployment and challenges of such an example system.

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Softwear: Software-Only in-memory wear-leveling for non-volatile main memory

arXiv

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arXiv 2020年

作者： Hakert, Christian Chen, Kuan-Hsun Genssler, Paul R. von der Brüggen, Georg Bauer, Lars Amrouch, Hussam Chen, Jian-Jia Henkel, Jörg Design Automation for Embedded Systems Group TU Dortmund Unibersity Germany Chair for Embedded Systems KIT Germany

Several emerging technologies for byte-addressable non-volatile memory (NVM) have been considered to replace DRAM as the main memory in computer systems during the last years. The disadvantage of a lower write endurance, compared to DRAM, of NVM technologies like Phase-Change Memory (PCM) or Ferroelectric RAM (FeRAM) has been addressed in the literature. As a solution, in-memory wear-leveling techniques have been proposed, which aim to balance the wear-level over all memory cells to achieve an increased memory lifetime. Generally, to apply such advanced aging-aware wear-leveling techniques proposed in the literature, additional special hardware is introduced into the memory system to provide the necessary information about the cell age and thus enable aging-aware wear-leveling decisions. This paper proposes software-only aging-aware wear-leveling based on common CPU features and does not rely on any additional hardware support from the memory subsystem. Specifically, we exploit the memory management unit (MMU), performance counters, and interrupts to approximate the memory write counts as an aging indicator. Although the software-only approach may lead to slightly worse wear-leveling, it is applicable on commonly available hardware. We achieve page-level coarse-grained wear-leveling by approximating the current cell age through statistical sampling and performing physical memory remapping through the MMU. This method results in nonuniform memory usage patterns within a memory page. Hence, we further propose a fine-grained wear-leveling in the stack region of C / C++ compiled software. By applying both wear-leveling techniques, we achieve up to 78.43% of the ideal memory lifetime, which is a lifetime improvement of more than a factor of 900 compared to the lifetime without any wear-leveling. Copyright © 2020, The Authors. All rights reserved.

关键词： C++ (programming language)

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Capacitor Minimization in Analog Synapses for Efficient and Compact Binarized SNNs

IEEE Transactions on Circuits and Systems for Artificial Int...

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IEEE Transactions on Circuits and systems for Artificial Intelligence 2025年第2期2卷 114-125页

作者： Mikail Yayla Ming-Liang Wei Simon Thomann Albi Mema Chia-Lin Yang Jian-Jia Chen Hussam Amrouch Design Automation for Embedded Systems Group TU Dortmund University Dortmund Germany Lamarr Institute for Machine Learning and Artificial Intelligence Dortmund Germany Department of the Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Technical University of Munich (TUM) Munich Germany TUM School of Computation Information and Technology Chair of AI Processor Design Munich Institute of Robotics and Machine Intelligence Munich Germany Department of Computer Science and Information Engineering Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Computer Science TU Dortmund University Dortmund Germany Lamarr Institute Dortmund Germany

Accelerating the immense workloads of Neural Networks (NNs) is a critical challenge, and analog computing-based approaches present a promising solution. Among these, the Integrate-and-Fire (IF) Spiking Neural Network (SNN) stands out for its potential in efficient neural computation. However, achieving high inference accuracy through precise multiply-accumulate (MAC) operations necessitates a large membrane capacitor—224 to 547 times larger than the synapse array at the 14nm technology node—resulting in prohibitive area costs. Additionally, the large capacitor size introduces higher energy consumption and longer access times. Thus, a key research challenge is maintaining accuracy while mitigating the costs associated with the large membrane capacitor. In this work, we propose a HW/SW Codesign method, called CapMin, for capacitor size minimization in analog computing IF-SNNs. CapMin minimizes the capacitor size by reducing the number of spike times needed for accurate operation of the HW, based on the absolute frequency of MAC level occurrences in the SW. To increase the operation of IF-SNNs to current variation, we propose the method CapMin-V, which trades capacitor size for protection based on the reduced capacitor size found in CapMin. In our experiments, CapMin achieves more than a 14 $\times$ reduction in capacitor size along with a 34% reduction in energy consumption over the state of the art, while CapMin-V achieves increased variation tolerance in the IF-SNN operation, requiring only a small increase in capacitor size.

关键词： Capacitors Circuits Accuracy Capacitance Micromechanical devices Costs Neurons Integrated circuit modeling Spiking neural networks Hardware

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Towards explainable bit error tolerance of resistive RAM-Based binarized neural networks

arXiv

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arXiv 2020年

作者： Buschjäger, Sebastian Chen, Jian-Jia Chen, Kuan-Hsun Günzel, Mario Hakert, Christian Morik, Katharina Novkin, Rodion Pfahler, Lukas Yayla, Mikail Artificial Intelligence Group TU Dortmund University Germany Design Automation for Embedded Systems Group TU Dortmund University Germany

Non-volatile memory, such as resistive RAM (RRAM), is an emerging energy-efficient storage, especially for low-power machine learning models on the edge. It is reported, however, that the bit error rate of RRAMs can be up to 3.3% in the ultra low-power setting, which might be crucial for many use cases. Binary neural networks (BNNs), a resource efficient variant of neural networks (NNs), can tolerate a certain percentage of errors without a loss in accuracy and demand lower resources in computation and storage. The bit error tolerance (BET) in BNNs can be achieved by flipping the weight signs during training, as proposed by Hirtzlin et al., but their method has a significant drawback, especially for fully connected neural networks (FCNN): The FCNNs overfit to the error rate used in training, which leads to low accuracy under lower error rates. In addition, the underlying principles of BET are not investigated. In this work, we improve the training for BET of BNNs and aim to explain this property. We propose straight-through gradient approximation to improve the weight-sign-flip training, by which BNNs adapt less to the bit error rates. To explain the achieved robustness, we define a metric that aims to measure BET without fault injection. We evaluate the metric and find that it correlates with accuracy over error rate for all FCNNs tested. Finally, we explore the influence of a novel regularizer that optimizes with respect to this metric, with the aim of providing a configurable trade-off in accuracy and *** Codes 68T05 Copyright © 2020, The Authors. All rights reserved.

关键词： Bit error rate

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Offloading safety- And mission-critical tasks via unreliable connections 32

Offloading safety- And mission-critical tasks via unreliable...

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32nd Euromicro Conference on Real-Time systems, ECRTS 2020

作者： Schönberger, Lea Chen, Kuan-Hsun Youssef, Hazem Wietfeld, Christian Chen, Jian-Jia von der Brüggen, Georg Sliwa, Benjamin Venkatapathy, Aswin Karthik Ramachandran ten Hompel, Michael Design Automation for Embedded Systems Group Faculty of Computer Science TU Dortmund University Germany Material Handling and Warehousing Faculty of Mechanical Engineering TU Dortmund University Germany Communication Networks Institute Faculty of Electrical Engineering TU Dortmund University Germany

ISBN: (纸本)9783959771528

For many cyber-physical systems, e.g., IoT systems and autonomous vehicles, offloading workload to auxiliary processing units has become crucial. However, since this approach highly depends on network connectivity and responsiveness, typically only non-critical tasks are offloaded, which have less strict timing requirements than critical tasks. In this work, we provide two protocols allowing to offload critical and non-critical tasks likewise, while providing different service levels for non-critical tasks in the event of an unsuccessful offloading operation, depending on the respective system requirements. We analyze the worst-case timing behavior of the local cyber-physical system and, based on these analyses, we provide a sufficient schedulability test for each of the proposed protocols. In the course of comprehensive experiments, we show that our protocols have reasonable acceptance ratios under the provided schedulability tests. Moreover, we demonstrate that the system behavior under our proposed protocols is strongly dependent on probability of unsuccessful offloading operations, the percentage of critical tasks in the system, and the amount of offloaded workload. © Lea Schönberger, Georg von der Brüggen, Kuan-Hsun Chen, Benjamin Sliwa, Hazem Youssef, Aswin Ramachandran, Christian Wietfeld, Michael ten Hompel, and Jian-Jia Chen.

关键词： Cyber Physical System

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Self-Awareness for Autonomous systems

引用

PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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Self-Stabilizing Micro Controller for Large-Scale Sensor Networks in Spite of Program Counter Corruptions Due to Soft Errors

Self-Stabilizing Micro Controller for Large-Scale Sensor Net...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Christopher Boelmann Torben Weis Michael Engel Arno Wacker Distributed Systems Group University of Duisburg-Essen Duisburg Germany Design Automation for Embedded Systems Group TU Dortmund University Dortmund Germany Software-engineering for Ubiquitous-Computing Applications University of Kassel Kassel Germany

For large installations of networked embedded systems it is important that each entity is self-stabilizing, because usually there is nobody to restart nodes that have hung up. Self-stabilization means to recover from temporary failures (soft errors) and adapt to a change of network topology caused by permanent failures. On the software side self-stabilizing algorithms must assume that the hardware is executing the software correctly. In this paper we discuss cases in which soft errors invalidate this assumption, especially in cases where CPU registers or the watchdog timer are affected by the fault. Based on the observation that a guaranteed self-stabilization is only possible as long as the watchdog-timer is working properly after temporary failures, we propose and compare three different approaches that meet the requirements of sensor networks, to solve this problem with a combination of hardware- and software-modifications: 1) A run-time verification of every watchdog access 2) A completely hardware-based approach, without any software modifications 3) A 2 X byte code alignment, to realign a corrupted program counter Furthermore we determine the average code-size increase and evaluate necessary hardware-modifications that come along with each approach.

关键词： Registers Hardware Random access memory Read only memory Microprocessors embedded systems

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Mapping embedded applications on MPSoCs: The MNEMEE approach

Lecture Notes in Electrical Engineering

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Lecture Notes in Electrical Engineering 2011年 105 LNEE卷 165-179页

作者： Baloukas, Christos Papadopoulos, Lazaros Soudris, Dimitrios Stuijk, Sander Jovanovic, Olivera Schmoll, Florian Marwedel, Peter Cordes, Daniel Pyka, Robert Mallik, Arindam Mamagkakis, Stylianos Capman, François Collet, Séverin Mitas, Nikolaos Kritharidis, Dimitrios 9 Iroon Polytechniou Street Athens 15773 Greece Eindhoven University of Technology Eindhoven Netherlands Design Automation for Embedded Systems Group TU-Dortmund Germany Informatik Centrum Dortmund E.V Dortmund Germany IMEC Vzw Leuven Belgium Thales Communications France 160 Boulevard de Valmy Colombes 92704 France Intracom Telecom Athens Greece

ISBN: (纸本)9789400714878

As embedded systems are becoming the center of our digital life, system design becomes progressively harder. The integration of multiple features on devices with limited resources requires careful and exhaustive exploration of the design search space in order to efficiently map modern applications to an embedded multi-processor platform. The MNEMEE project addresses this challenge by offering a unique integrated tool flow that performs source-to-source transformations to automatically optimize the original source code and map it on the target platform. The optimizations aim at reducing the number of memory accesses and the required memory storage of both dynamically and statically allocated data. Furthermore, the MNEMEE tool flow parallelizes the application's source code and performs optimal assignment of all data on the memory hierarchy of the target platform. designers can use the whole flow or a part of it and integrate it into their own design flow. This work gives an overview of the MNEMEE tool flow. It also presents two industrial case studies that demonstrate how the techniques and tools developed in the MNEMEE project can be integrated into industrial design flows. © 2011 Springer Science+Business Media B.V.

关键词： Optimal systems

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