In this paper, we have shown that off-state current in the tunneling field effect transistor (TFET) can be reduced dramatically by using an ¿asymmetric¿ gate oxide thickness and employing gate work function ...
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In this paper, we have shown that off-state current in the tunneling field effect transistor (TFET) can be reduced dramatically by using an ¿asymmetric¿ gate oxide thickness and employing gate work function engineering. This procedure does not affect driving current while reduces I off by 5 orders magnitude, hence obtained the noticeable of I on /I off ratio. We discuss optimization of I on /I off ratio and investigate the effect of scaling on the I on /I off ratio in the proposed structure.
A double gate p-IMOS (DG p-IMOS) as well as a process definition for this device is proposed. simulation studies show that at 400 (K) this device provides smaller subthreshold slope and threshold voltage than a single...
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A double gate p-IMOS (DG p-IMOS) as well as a process definition for this device is proposed. simulation studies show that at 400 (K) this device provides smaller subthreshold slope and threshold voltage than a single...
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A double gate p-IMOS (DG p-IMOS) as well as a process definition for this device is proposed. simulation studies show that at 400 (K) this device provides smaller subthreshold slope and threshold voltage than a single gate p-IMOS (SG p- IMOS). The ON/OFF current ratio for the DG p-IMOS is larger than that of an equivalent SG p-IMOS. Moreover, the double gate device has higher transconductance than the single gate device. The DG p-IMOS structural parameters affect its electrical characteristics. Reduction of the body thickness tends to lower threshold voltage and increase ON/OFF current ratio. Furthermore, for a given spacing between source and drain threshold voltage reduces as the gate length is increased.
Over the past few decades, CMOS has proved to be the choice device in the fabrication of the high density integrated circuits. However, in this technology the device performance is degraded primarily due to mobility l...
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Over the past few decades, CMOS has proved to be the choice device in the fabrication of the high density integrated circuits. However, in this technology the device performance is degraded primarily due to mobility limitation in PMOS transistors. One way to elevate this problem is to alter electronic properties of the channel region, so that the hole mobility is increased. It is possible to enhance electronic properties of the channel region using strained layers. It has been shown that when a thin epitaxial film of Si{sub}(1-x)Ge{sub}x layer is grown on top of a silicon substrate, a compressive strain is induced in Si{sub}(1-x)Ge{sub}x layer due to the mismatch between Si and SiGe layer and the hole mobility in the strained layer is increased. This result is due to a reduction of the interband scattering and the consequent reduction of the inplane hole effective mass [1], [2],[3]. An important parameter for this structure is the Ge mole fraction in the Si{sub}(1-x)Ge{sub}x layer, which not only defines the valence band offset (△E{sub}V) at Si/Si{sub}(1-x)Ge{sub}x heterointerface but also the hole mobility in the two-dimensional hole gas(2-DHG). As the gate voltage becomes more negative, holes accumulate first at Si/SiGe interface. Thus threshold voltage (V{sub}(TH)) is defined as the gate voltage at which depletion layer width reaches its maximum value (W=W{sub}(MAX)). Under this condition an inversion layer is created at Si/SiGe interface (x=t{sub}(cap)). For |V{sub}G|>|V{sub}(TH)| the sheet hole concentration ((ρ{sub}s){sup}H) at the heterointerface increases. If the gate voltage is increased up to V{sub}G=V{sub}(TS), another inversion layer is produced at SiO{sub}2/Si interface [1].
A circuit design style with separate logic and buffer tages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply ...
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