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arXiv 2020年

作者： Rassekh, Amin Sallese, Jean-Michel Jazaeri, Farzan Fathipour, Morteza Ionescu, Adrian M. Switzerland Ecole Polytechnique Fdrale de Lausanne Switzerland Device Simulation and Modeling Laboratory Department of Electrical and Computer Engineering University of Tehran

In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, for the first time, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 µA/µm). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation. Copyright © 2020, The Authors. All rights reserved.

关键词： Field effect transistors

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modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects

arXiv

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arXiv 2019年

作者： Rassekh, Amin Jazaeri, Farzan Fathipour, Morteza Sallese, Jean-Michel Ecole Polytechnique Fédérale de Lausanne Switzerland device simulation and modeling Laboratory department of electrical and computer engineering University of Tehran Iran

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation. Copyright © 2019, The Authors. All rights reserved.

关键词： Ionizing radiation

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A numerical study of a new four-layer-substrate closing device

A numerical study of a new four-layer-substrate closing devi...

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Iranian Conference on Electrical Engineering (ICEE)

作者： Tara Afra Seyed Nasrolah Anousheh Ahmad Taghinia Morteza Fathipour Electrical Engineering Department Islamic Azad University Tehran Iran Device Modeling and Simulation Laboratory Tehran university Tehran Iran

Creating high power electrical pulses with sub nanosecond rise time is possible by using fast impact ionization process in closing four-layer-substrate devices. Fast impact ionization in semiconductor devices is one of the quickest non-optical pulse generation methods even in the range of less than nanosecond. In this paper electron-hole plasma generation and fast impact ionization mechanism of a four-layer-substrate device would be discussed by using numerical study and also physical model, Effective factors such as impurity concentration and substrate thickness in switching velocity, current peak, generated electron-hole plasma and residual voltage in device. This study provides several optimized characteristics in these switches.

关键词： Plasmas Substrates Impact ionization Impurities Electric fields Semiconductor process modeling

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An investigation in the impact of structural parameters on the electrical characteristics of Nanoscale Heterostructure P-MOSFETs

An investigation in the impact of structural parameters on t...

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IEEE International Conference on Semiconductor Electronics (ICSE)

作者： Fatemeh Kohani Khoshkbijari Reza Fouladi Shiva Nejati Reza Barkhordari Reza Kohani Khoshkbijari Shide Nejati Device Simulation and Modeling Laboratory Sama Technical and Vocational Training College Islamic Azad University Rasht Iran

Over the past few decades, CMOS has proved to be the choice device in the fabrication of the high density integrated circuits. However, in this technology the device performance is degraded primarily due to mobility limitation in PMOSFET. One way to elevate this problem is to alter electronic properties of the channel region using strained layers. In this paper, we propose a novel Heterosructure PMOSFETs with optimum Ge content in SiGe layer. This investigation proves that an increase in Ge mole fraction reduces threshold voltage on Si/SiGe interface, while threshold voltage on Si/SiO 2 is increased. As the Ge mole fraction is increased the gate capacitance also will increase. The results provide useful guide lines for optimizing Nanoscale Heterostructure for low power applications.

关键词： Silicon MOSFET circuits Silicon germanium Logic gates Threshold voltage Substrates Electron devices

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Improvement of short channel effects in cylindrical strained silicon nanowire transistor

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World Academy of Science, Engineering and Technology 2010年 69卷 467-470页

作者： Karimi, Fatemeh Fathipour, Morteza Ghanatian, Hamdam Fathipour, Vala Islamic Azad University Central branch Tehran Iran Device and Simulation Lab. IEEE Department of Electrical and Computer Engineering University of Tehran P.O. Box 14395-515 Tehran Iran Device Modeling and Simulation Laboratory Department of Electrical and Computer Engineering University of Tehran Iran

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

关键词： Gate dielectrics

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The analysis of photoconductive semiconductor switch operation in the frequency of 10GHz

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World Academy of Science, Engineering and Technology 2010年 69卷 458-462页

作者： Fathipour, Morteza Anousheh, Seyed Nasrolah Davoudi, Kaveh Ghiafeh Fathipour, Vala Device and Simulation Lab IEEE Department of Electrical and Computer Engineering University of Tehran P.O. Box 14395-515 Tehran Iran Department of Electrical and Computer Engineering Islamic Azad University-Central Tehran Branch Tehran Iran Device Modeling and Simulation Laboratory Department of Electrical and Computer Engineering University of Tehran Iran

A device analysis of the photoconductive semiconductor switch is carried out to investigate distribution of electric field and carrier concentrations as well as the current density distribution. The operation of this device was then investigated as a switch operating in X band. It is shown that despite the presence of symmetry geometry, switch current density of the on-state steady state mode is distributed asymmetrically throughout the device.

关键词： Photoconductivity

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The impact of process parameters on the output characteristics of an LDMOS device

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World Academy of Science, Engineering and Technology 2010年 69卷 471-474页

作者： Malakoutian, M.A. Fathipour, V. Fathipour, M. Mojab, A. Allame, M.M. Moradinasab, M. Department of Electrical and Computer Engineering University of Tehran P.O. Box 14395-515 Tehran Iran Device Modeling and Simulation Laboratory Department of Electrical and Computer Engineering University of Tehran Iran

In this paper, we have examined the effect of process parameter variation on the electrical characteristics of an LDMOS device. The rate of change in the electrical parameters such as cut off frequency, breakdown volt... 详细信息

关键词： Drain current

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AC analysis of UMOSFET ACCUFET

AC analysis of UMOSFET ACCUFET

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International Symposium Semiconductor device Research (ISDRS)

作者： N. Peyvast M. Fathipour Device and Process Modeling and Simulation Laboratory School of Electrical and Computer Engineering University of Tehran Tehran Iran

In this paper, the structure of a power UMOSFET ACCUFET has been investigated. For a given device length when the number of trenches is increased transconductance increases as the cut off frequency does. The effect of such a design on the conductance of the device is investigated and demonstrated that the conductance of this device can be improved by as large as 600% at the gate and drain voltage of 10 volts.

关键词： Voltage Silicon carbide Frequency Transconductance Proximity effect Educational institutions Electron mobility Computational modeling Analytical models Computer simulation

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A novel 4H-SiC UMOSFET_ACCUFET with large blocking voltage

A novel 4H-SiC UMOSFET_ACCUFET with large blocking voltage

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Asia Symposium on Quality Electronic Design, ASQED

作者： Negin Peyvast Morteza Fathipour Device and Process Modeling and Simulation Laboratory School of Electrical and Computer Engineering University of Tehran Tehran Iran

In this paper, a new structure for a power UMOSFET_ACCUFET, based-on 4H-SiC, has been represented. We have demonstrated that by using vertical P and N pillars under the trench of a conventional UMOSFET, a superior characteristic for this device is achieved. The structure may be optimized by appropriate choice of N and P pillar's doping concentrations as well as widths.

关键词： Voltage Electric breakdown Doping Electric resistance Electrons Thermal conductivity Protection MOSFET circuits Guidelines Computational modeling

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The impact of structural parameters on the electrical characteristics of GAA Silicon nanowire transistor

The impact of structural parameters on the electrical charac...

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International Symposium Semiconductor device Research (ISDRS)

作者： M. Fathipour F. Karimi R. Hosseini Device Modeling and Simulation Laboratory ECE Department University of Tehran Tehran Iran Central branch Islamic Azad University Tehran Iran Science & Research branch Islamic Azad University Tehran Iran

In this paper we investigate the electrical characteristics of silicon nanowire transistors using a fully ballistic quantum mechanical transport approach to analyze rectangular silicon nanowire transistor. We investigate the impact of structural parameters of nano scale Gate all around Silicon nano wire transistor (GAA-SNWT)on its electrical characteristics in subthreshold regime. In particular we show that increase in Source/Drain length (Ls ,LD) negligibly affects the current while increasing the Ls/LD will affect the gate capacitance. We also investigate the effect of increasing the gate underlap on short channel effects and on the switching speed of device. We show that if the L ¿¿¿ is increased the gate capacitance and DIBL will reduces while the Ion/Ioff ratio is increased. This parameter affect the power consumption and delay and is useful in nanowire design for low power application.

关键词： Structural engineering Electric variables Silicon Wire Nanoscale devices Educational institutions Quantum mechanics Quantum capacitance Delay Green's function methods

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