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2011 - International Conference on Signal processing, Communication, Computing and Networking Technologies, ICSCCN-2011

作者： Rajabi, Saba Orouji, Ali A. Moghadam, Hamid Amini Mahabadi, S.E. Jamali Fathipour, Morteza Electrical Engineering Department Semnan University Semnan Iran Device Modeling and Simulation Lab. Electrical Engineering Department Tehran University Tehran Iran

ISBN: (纸本)9781612846538

In this paper, we have investigated the effectiveness of employing the drain field-plate technique to enhance the breakdown voltage of single source field-plate (SSFP) AlGaN/GaN power high electron mobility transistors (HEMTs). A systematic procedure is provided for designing this new double drain and source field-plate (DDSFP) structure, using two dimensional simulation to achieve the maximum improvement in the drain-source current (IDS) and breakdown voltage (BV). It is found that significantly higher BV and IDS can be achieved by just optimizing the thickness of the passivation layer Si 3N4 beneath the field plates and the length of field plates connected to the source and drain. The effects of the substrate superjunction layers thickness and the gate recess depth on the BV are also studied. © 2011 IEEE.

关键词： High electron mobility transistors

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A novel power high electron mobility transistor with partial stepped recess in the drain access region for performance improvement

A novel power high electron mobility transistor with partial...

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2011 - International Conference on Signal processing, Communication, Computing and Networking Technologies, ICSCCN-2011

ISBN: (纸本)9781612846538

In this letter, we proposed a new power High Electron Mobility Transistor (HEMT) with partial stepped recess in the drain access region. This approach represents a new way to increase the breakdown voltage by 100%, which is very important in higher voltage applications. The use of drain access region recesses allows a 43% decrease of the peak electric field and only a 1.91% increase of the drain access resistance which is negligible. The proposed structure shows an improvement in the maximum oscillation frequency (f max) and cut-off frequency (fT) over the conventional structure. © 2011 IEEE.

关键词： High electron mobility transistors

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A novel AlGaN/GaN/AlGaN double-heterojunction high electron mobility transistor for performance improvement

A novel AlGaN/GaN/AlGaN double-heterojunction high electron ...

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2011 - International Conference on Signal processing, Communication, Computing and Networking Technologies, ICSCCN-2011

ISBN: (纸本)9781612846538

In this paper, we present an enhancement of breakdown voltage in AlGaN/GaN/AlGaN double-heterojunction high-electron-mobility-transistor devices by introducing a magnesium doping layer in AlGaN buffer layer under the 2DEG channel. The optimized electron confinement and mitigated electric field peak under the drain side of the gate in DH-HEMT along with more evenly distributed electric field due to the presence of a charge balanced magnesium doping layer result in significant breakdown voltage improvement and subthreshold gate and drain leakage currents suppression. The introduced magnesium doping layer acts as a floating field plate. By optimizing the length of this float field plate, the breakdown voltage will increase by 90.5%, which is very important in higher voltage applications. This approach also allows a 33% decrease of the peak electric field under the drain side edge of the gate while the ON-state resistance is negligibly increased. © 2011 IEEE.

关键词： High electron mobility transistors

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Improvement of short channel effects in cylindrical strained silicon nanowire transistor

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World Academy of Science, Engineering and Technology 2010年 69卷 467-470页

作者： Karimi, Fatemeh Fathipour, Morteza Ghanatian, Hamdam Fathipour, Vala Islamic Azad University Central branch Tehran Iran Device and Simulation Lab. IEEE Department of Electrical and Computer Engineering University of Tehran P.O. Box 14395-515 Tehran Iran Device Modeling and Simulation Laboratory Department of Electrical and Computer Engineering University of Tehran Iran

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

关键词： Gate dielectrics

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AC analysis of UMOSFET ACCUFET

AC analysis of UMOSFET ACCUFET

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2009 International Semiconductor device Research Symposium, ISDRS '09

作者： Peyvast, N. Fathipour, M. Device and Process Modeling and Simulation Lab. School of Electrical and Computer Eng. University of Tehran Kargar Ave. Tehran Iran

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The impact of structural parameters on the electrical characteristics of GAA silicon nanowire transistor

The impact of structural parameters on the electrical charac...

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2009 International Semiconductor device Research Symposium, ISDRS '09

作者： Fathipour, M. Karimi, F. Hosseini, R. Device Modeling and Simulation Lab. ECE Dept. University of Tehran Tehran Iran Islamic Azad University Central Branch Tehran Iran Islamic Azad University Science and Research Branch Tehran Iran

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A novel nanoscale tunnel FET structure for increasing on/off current ratio

A novel nanoscale tunnel FET structure for increasing on/off...

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International Conference on Microelectronics, ICM

作者： Mahdi Vadizadeh Morteza Fathipour Arash Amid Device and Process Modeling and Simulation Lab University of Tehran Tehran Iran Dept of Electrical and Computer Engineering University of Tehran

In this paper, we have shown that off-state current in the tunneling field effect transistor (TFET) can be reduced dramatically by using an ¿asymmetric¿ gate oxide thickness and employing gate work function engineering. This procedure does not affect driving current while reduces I off by 5 orders magnitude, hence obtained the noticeable of I on /I off ratio. We discuss optimization of I on /I off ratio and investigate the effect of scaling on the I on /I off ratio in the proposed structure.

关键词： Nanostructures FETs Microelectronics

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A comparison study between double and single gate p-IMOS

A comparison study between double and single gate p-IMOS

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IEEE AFRICON 2007

作者： Hassani, F.A. Fathipour, M. Mehran, M. Device Modeling and Simulation Lab. ECE Dept. University of Tehran

ISBN: (纸本)142440987X

A double gate p-IMOS (DG p-IMOS) as well as a process definition for this device is proposed. simulation studies show that at 400 (K) this device provides smaller subthreshold slope and threshold voltage than a single gate p-IMOS (SG p-IMOS). The ON/OFF current ratio for the DG p-IMOS is larger than that of an equivalent SG p-IMOS. Moreover, the double gate device has higher transconductance than the single gate device. The DG p-IMOS structural parameters affect its electrical characteristics. Reduction of the body thickness tends to lower threshold voltage and increase ON/OFF current ratio. Furthermore, for a given spacing between source and drain threshold voltage reduces as the gate length is increased. ©2007 IEEE.

关键词： Threshold voltage

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