In this paper, a new structure for a power UMOSFET_ACCUFET, based-on 4H-SiC, has been represented. We have demonstrated that by using vertical P and N pillars under the trench of a conventional UMOSFET, a superior cha...
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In this paper, a new structure for a power UMOSFET_ACCUFET, based-on 4H-SiC, has been represented. We have demonstrated that by using vertical P and N pillars under the trench of a conventional UMOSFET, a superior characteristic for this device is achieved. The structure may be optimized by appropriate choice of N and P pillar's doping concentrations as well as widths.
In this paper, the structure of a power UMOSFET ACCUFET has been investigated. For a given device length when the number of trenches is increased transconductance increases as the cut off frequency does. The effect of...
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In this paper, the structure of a power UMOSFET ACCUFET has been investigated. For a given device length when the number of trenches is increased transconductance increases as the cut off frequency does. The effect of such a design on the conductance of the device is investigated and demonstrated that the conductance of this device can be improved by as large as 600% at the gate and drain voltage of 10 volts.
In order to improve the electrical characteristics of Schottky barrier p-MOSFETs with strained channel, we have proposed to reduce silicon-cap thickness in this paper. We demonstrate in the proposed hetero SBMOS, by d...
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In order to improve the electrical characteristics of Schottky barrier p-MOSFETs with strained channel, we have proposed to reduce silicon-cap thickness in this paper. We demonstrate in the proposed hetero SBMOS, by decreasing the silicon-cap from 10 nm to 4 nm, the I on /I off ratio and transconductance can be improved up to 98% and 20% respectively.
In order to decrease bias voltages in IMOS devices we have proposed a new IMOS structure with Si-Ge/Si heterostructure channel in this paper. In comparison with previously reported, single gate SOI IMOS and SGOI IMOS ...
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In order to decrease bias voltages in IMOS devices we have proposed a new IMOS structure with Si-Ge/Si heterostructure channel in this paper. In comparison with previously reported, single gate SOI IMOS and SGOI IMOS structures, this device can provide higher reduction in the source voltage as well as in threshold voltage. Moreover, the proposed structure provides considerable reduction in off-state current, while preserving the on-state current.
作者：
Shimizu, STanizawa, MKusunoki, SInuishi, MMiyoshi, HULSI Laboratory
Mitsubishi Electric Corporation 4-1 Mizuhara Itami Hyogo Japan 664 Received the B.S. and M.S. degrees in electronic engineering from Kobe University
Hyogo Japan in 1988 and 1990 respectively. In 1990 he joined LSI Research and Development Laboratory Mitsubishi Electric Corporation where he has been engaged in research on the structural design of submicron CMOS such as MOSFETs silicidation and reliability including investigations of the hot carrier effect in the ULSI Laboratory. He is a member of the Japan Society of Applied Physics. Received the B.S. and M.S. degrees in electronic engineering from Kyoto University
Kyoto Japan in 1983 and 1985 respectively. From 1985 to 1988 he was with Sharp Corporation Nara Japan. In 1988 he joined LSI Research and Development Laboratory Mitsubishi Electric Corporation Hyogo Japan where he has been engaged in semiconductor device modeling for circuit simulation in ULSI Laboratory. He is a member of the Japan Society of Applied Physics. Received the B.S. degree in Physics and the M.S. degree in Information Systems Science from Kyushu University in 1978 and 1982
respectively. He joined the LSI Research and Developmept Laboratory Mitsubishi Electric Corporation Hyogo Japan in 1982. From 1982 to 1988 he was engaged in research on SOI device technology and three-dimensional ICs and from 1988 to 1995 he was engaged in research on the structural design of scaled MOS transistors. He is presently engaged in the research on the structural design of power devices in the ULSI Laboratory. He is a member of the Japan Society of Applied Physics. Received a B.S. in materials science and engineering from Osaka University
Japan in 1976 and a Ph.D. from Northwestern University Evanston Illinois in 1981. In 1981 he joined LSI Research and Development Laboratory Mitsubishi Electric Corporation Hyogo Japan. Since then he has been engaged in research on process and device technologies for 64K and 1M DRAMs and on submicron CMOS isolation ret
High performance under low supply voltage is required for ULSIs in combination with the higher packing density that results from scaling down to the deep sub-micron region. For this requirement, the conventional metho...
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High performance under low supply voltage is required for ULSIs in combination with the higher packing density that results from scaling down to the deep sub-micron region. For this requirement, the conventional method, using the DC hot carrier lifetime of MOSFETs as measured by DC stress, overestimates the degradation caused by real circuit operation. As a result, the improvement of MOSFET performance is limited by attempting to satisfy the overestimated hot carrier criteria under DC stress. Therefore, it is strongly desired that the reliability simulation estimate accurately hot carrier degradation in real circuit operation. We have found that the degradation rate depends on the stress conditions and can be expressed in terms of the difference between the gate and drain voltages. Hence, in this paper, we propose a new method of modeling and calculation of hot carrier degradation that incorporates this dependence and will demonstrate improved accuracy in predicting degradation and life time for both AC and DC bias conditions. We also propose a new duty ratio extraction method that can be used to predict the lifetime for hot carrier degradation under actual circuit operation.
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