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IET Blockchain 2022年第1期2卷 1-12页

作者： Iliakis, Konstantinos Koliogeorgi, Konstantina Litke, Antonios Varvarigou, Theodora Soudris, Dimitrios Microprocessors and Digital Systems Laboratory Department of Electrical and Computer Engineering National Technical University of Athens Zografou Campous 9 Iroon Polytechniou str Athens Greece Distributed Knowledge and Media Systems group Department of Electrical and Computer Engineering National Technical University of Athens Zografou Campous 9 Iroon Polytechniou str Athens Greece

Blockchain is a distributed ledger based on peer-to-peer networks, originally used for crypto-currency systems. Blockchains are being used as an enabling technology for decentralised applications in the areas of Internet-of-Things, finance, supply-chain and others. Consistency, data privacy, performance, and energy efficiency are of paramount importance in such applications. The full nodes of public, permissionless blockchains undertake the task of verifying the transactions generated by the network. Full nodes perform operations such as confirming balances, transactions, and history, i.e. mostly database search queries. Consequently, their throughput is crucial for the performance of blockchain systems. In this work, the benefits of accelerating the blockchain search and insert queries by leveraging GPU platforms are studied. An extensive comparison between the most dominant utilized database is provided, i.e. LevelDB, and MegaKV, a high-performance GPU-accelerated database. Realistic operations that take place in blockchain systems are emulated and evaluated over representative scenarios, showing three orders of magnitude gains in throughput and energy efficiency without compromising the security aspect. The extensive comparison between LevelDB and MegaKV indicates that GPU acceleration is an effective solution for runtime and energy efficiency enhancement of blockchain systems, and the integration of the two technologies is a promising field of research. © 2022 The Authors. IET Blockchain published by John Wiley & Sons Ltd on behalf of The Institution of engineering and Technology.

关键词： Blockchain

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Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design

Combined Split Manufacturing and Logic Obfuscation Based on ...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Haimanti Chakraborty Ranga Vemuri Electrical and Computer Engineering Department Digital Design Environments Laboratory University of Cincinnati Cincinnati Ohio USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

Split Manufacturing (SM) and Logic Obfuscation (LO) are potent design-for-trust solutions to mitigate hardware security threats when fabricating Integrated Circuits (ICs) at untrusted foundries. However, many such defense methods are subject to attacks such as Network Flow Attack and Boolean Satisfiability Attack, that have attempted to reconstruct the missing BEOL (Back End Of Line) signals and decrypt the design. Hence, it is crucial to select BEOL signals carefully. Although several defense strategies have been proposed to protect the design against the attacks, many have been implemented at lower abstraction levels that incur expensive re-synthesis cycles. In this paper, we combine SM and LO for enhanced security of 3D ICs by proposing a BEOL signal selection method at high level based on assigning edge-weights to prioritize Data Flow Graph edges, that also identify locations for Polymorphic Switch Boxes (PSBs) for LO. A PSB has more key-bit combinations compared to a CMOS SB for an attacker to correctly unlock it. Our method decreases attack correctness with increase in the percentage of edges lifted and has minimal impact on design performance in terms of area and wirelength.

关键词： Three-dimensional displays Circuits and systems Hardware security Switches Foundries Manufacturing Logic

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Fine-tuning Specialized NER Model for Symptom Extraction from Slovenian Medical Texts

Fine-tuning Specialized NER Model for Symptom Extraction fro...

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International Conference on Mathematics and computers in Sciences and in Industry (MCSI)

作者： Rigon Sallauka Umut Arioz Izidor Mlakar Laboratory of Digital Signal Processing University of Maribor Faculty of Electrical Engineering and Computer Science Maribor Slovenia

ISBN: (数字)9798350377224

ISBN: (纸本)9798350377231

In this study, we aim to develop a robust model capable of accurately extracting symptoms from clinical texts written in the Slovenian language. Our methodology involves several steps to achieve this objective. Initially, we identify datasets containing clinical texts in English and select a specialized model designed for symptom extraction from these texts. Then, we annotate the datasets and undertake the translation process into Slovenian, ensuring the preservation of annotations to maintain data integrity. Utilizing the translated dataset, we proceed to fine-tune the selected model specifically for Slovenian texts. Despite our efforts, optimal performance has not yet been attained. Challenges encountered include the translation methodology employed and the architectural limitations of the chosen model, which is primarily optimized for English texts. However, ongoing efforts are underway to address these challenges and enhance the model's performance. Our study represents a step towards improving automated symptom extraction in Slovenian clinical texts, with ongoing work focused on mitigating identified issues to achieve better outcomes.

关键词： Adaptation models Translation Accuracy Text analysis Annotations Computational modeling Data models Mathematical models Reliability Tuning

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RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation

RTL Interconnect Obfuscation By Polymorphic Switch Boxes For...

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IEEE International Symposium on Quality Electronic Design

作者： Haimanti Chakraborty Ranga Vemuri Electrical and Computer Engineering Department Digital Design Environments Laboratory University of Cincinnati Cincinnati Ohio USA

ISBN: (数字)9798350309270

ISBN: (纸本)9798350309287

Logic Obfuscation is a well renowned design-for-trust solution to protect an Integrated Circuit (IC) from unauthorized use and illegal overproduction by including key-gates to lock the design. This is particularly necessary for ICs manufactured at untrusted third-party foundries getting exposed to security threats. In the past, several logic obfuscation methodologies have been proposed that are vulnerable to attacks such as the Boolean Satisfiability Attack. Many of these techniques are implemented at the gate level that may involve expensive re-synthesis cycles. In this paper, we present an interconnect obfuscation scheme at the Register-Transfer Level (RTL) using Switch Boxes (SBs) constructed of Polymorphic Transistors. A polymorphic SB can be designed using the same transistor count as its Complementary-Metal-Oxide-Semiconductor based counterpart, thereby no increased area in comparison, but serving as an advantage in having more key-bit combinations for an attacker to correctly identify and unlock each polymorphic SB. Security-aware high-level synthesis algorithms have also been presented to increase RTL interconnects to Functional Units impacting multiple outputs such that when a polymorphic SB is strategically inserted, those outputs would be corrupted upon incorrect keybit identification. Finally, we run the SMT (Satisfiability Modulo Theories)-based RTL Logic Attack on the obfuscated design to examine its robustness.

关键词： Job shop scheduling Integrated circuit interconnections Switches Logic gates Robustness Hardware Transistors

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ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors

ROBUST: RTL OBfuscation USing Bi-functional Polymorphic Oper...

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International Conference on VLSI Design

作者： Haimanti Chakraborty Ranga Vemuri Electrical and Computer Engineering Department Digital Design Environments Laboratory University of Cincinnati Cincinnati Ohio USA

Manufacturing Integrated Circuits (ICs) at untrusted third-party foundries has introduced security vulnerabilities. Logic Obfuscation is a well known design-for-trust solution that can prevent unauthorized use and overproduction of ICs by means of adding extra key-gates to lock the design. Several logic locking techniques proposed in the past have incurred performance overheads and are vulnerable to attacks such as the Boolean Satisfiability Attack. Many of these logic obfuscation methodologies have been implemented at the gate level that may involve expensive re-synthesis cycles. In this paper, we propose a logic obfuscation scheme at the Register-Transfer Level (RTL) by using bi-functional polymorphic logic gates to construct the Functional Units (FUs) of operation, and the proposed technique does not increase the area overhead significantly. A bi-functional FU is capable of saving resources by computing more than one ALU (Arithmetic-Logic Unit) operation by itself and also helps increase confusion for an attacker to identify which interconnections would belong to which operator of the bi-functional FU. Security-aware high-level synthesis algorithms have also been presented to allocate Data Flow Graph nodes to the polymorphic FUs. Additionally, we include a multiplier block in a polymorphic FU for increased robustness against the SMT (Satisfiability Modulo Theories)-based RTL Logic Attack.

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CharLib: An Open Source Standard Cell Library Characterizer

CharLib: An Open Source Standard Cell Library Characterizer

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Marcus Mellor James E. Stine Electrical and Computer Engineering Department VLSI Computer Architecture Research Laboratory Oklahoma State University Stillwater OK USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

With the current rise in popularity of open source silicon design there is a need for low-cost high-quality SoC design tools. This paper presents an open-source python-based standard cell library char-acterizer compatible with combinational and sequen-tial cells. This characterizer can be configured from a single YAML file, reducing the complexity of the char-acterization process for silicon designers and enabling repeatable characterization through easy integration with existing version control tools. The characterizer generates a liberty file for the cell library that can be used by other EDA tools. The tool is compared to a com-mercial characterizer using an open-source PDK. Timing results are within 1 nanosecond mean absolute er-ror compared to commercial characterization tools.

关键词： Micrometers Accuracy Circuits and systems Process control Libraries Silicon Design tools

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Implementing digital Twins for Enhanced Energy Management in Three Case Studies

Implementing Digital Twins for Enhanced Energy Management in...

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2024 IEEE International Workshop on Metrology for Living Environment, MetroLivEnv 2024

作者： Testasecca, Tancredi Stamatopoulos, Stathis Natalini, Andrea Lazzaro, Marilena Capizzi, Chiara Maria Sarmas, Elissaios Arnone, Diego Università degli Studi di Palermo Dipartimento di Ingegneria Palermo Italy School of Electrical & Computer Engineering National Technical University of Athens Decision Support Systems Laboratory Athens Greece Engineering Ingegneria Informatica S.p.A. Digital Twin and IOT Solutions Department Rome Italy Digital Hubs Engineering Ingegneria Informatica S.p.A. Palermo Italy

ISBN: (纸本)9798350385014

digitalization is recognized as a powerful enabler for decarbonizing the building sector. The International Energy Agency has highlighted its potential to improve safety, productivity, accessibility, and sustainability of energy systems. This work aims to present innovative applications of digital twins within the European Project DigiBUILD, focusing on optimizing energy systems for enhanced efficiency and reduced carbon footprint. The architecture of the developed digital twins w detailed, focusing on data collection, services description, and their implementation. Through three detailed case studies, the paper explores real applications of digital twins: the Heron pilot, whose aim is to manage a cluster of buildings and optimally charges electric vehicles to reduce carbon emissions;Veolia, where a district heating networks to optimally manage heat sources in the production plant to reduce gas consumption and emissions;and Emotion, focusing on a building equipped with photovoltaic panels and electric vehicles and implementing services for optimal vehicle charging to maximize self-consumption, in day-ahead scheduling but also in real time. A discussion finally highlights the challenges and limitations encountered in the deployment of digital twins, emphasizing the importance of user interaction in facilitating efficient energy management. This research contributes in underlining the significant potential of digital twins in advancing the digitalization of the energy sector, contributing to the European Union's goals for sustainability and reduced environmental impact. © 2024 IEEE.

关键词： Carbon footprint

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Progressive Motion Boosting for Video Frame Interpolation

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IEEE Transactions on Multimedia 2023年 25卷 8076-8090页

作者： Xiao, Jing Xu, Kangmin Hu, Mengshun Liao, Liang Wang, Zheng Lin, Chia-Wen Wang, Mi Satoh, Shin'Ichi The School of Computer Science Wuhan University Wuhan430072 China The School of Computer Science and Engineering Nanyang Technological University Singapore639798 Singapore The Department of Electrical Engineering the Institute of Communications Engineering National Tsing Hua University Hsinchu30013 Taiwan The State Key Laboratory of Information Engineering in Surveying Mapping and Remote Sensing Wuhan University Wuhan430072 China The Digital Content and Media Sciences Research Division National Institute of Informatics Tokyo101-8430 Japan

Video frame interpolation has made great progress in estimating advanced optical flow and synthesizing in-between frames sequentially. However, frame interpolation involving various resolutions and motions remains challenging due to limited or fixed pre-trained networks. Inspired by the success of the coarse-to-fine scheme for video frame interpolation, i.e., gradually interpolating frames of different resolutions, we propose a progressive boosting network (ProBoost-Net) based on a multi-scale framework to achieve flexible recurrent scales and then gradually optimize optical flow estimation and frame interpolation. Specifically, we designed a dense motion boosting (DMB) module to transfer features close to real motion to the decoded features from the later scales, which provides complementary information to refine the motion further. Furthermore, to ensure the accuracy of the estimated motion features at each scale, we propose a motion adaptive fusion (MAF) module that adaptively deals with motions with different receptive fields according to the motion conditions. Thanks to the framework’s flexible recurrent scales, we can customize the number of scales and make trade-offs between computation and quality depending on the application scenario. Extensive experiments with various datasets demonstrated the superiority of our proposed method over state-of-the-art approaches in various scenarios. © 2023 Institute of electrical and Electronics Engineers Inc.. All rights reserved.

关键词： Motion estimation

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Aorta localization in Computed Tomography images: A YoloV9 segmentation approach

Aorta localization in Computed Tomography images: A YoloV9 s...

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South Eastern European Design Automation, computer engineering, computer Networks and Social Media Conference (SEEDA-CECNSM)

作者： Panagiotis N. Smyrlis Gabriela R. Stancu Foteini Dimaraki Aimilia Ntetska Thomai Karamitsou Katerina D. Tzimourta Markos G. Tsipouras Pantelis Angelidis Laboratory of Biomedical Technology and Digital Health School of Electrical and Computer Engineering University of Western Macedonia Kozani Greece

ISBN: (数字)9798331504489

ISBN: (纸本)9798331504496

In this study, state-of the art segmentation methods were tested for use in biomedical CTA images to precisely highlight aorta instances. A set of YOLO architectures was trained on a newly annotated dataset of 120 transverse view images and detailed cross-validation results were obtained to measure the detection and precise localization ability of the models. The recent YOLOV9 algorithm flavors V9-C and V9-E were studied and compared to the previous V8-X model. The V9 version did score remarkable results to Mean Average Precision metrics, achieving 76.15% segmentation mAP50-95 score in the YOLOV9-C testing.

关键词： YOLO Location awareness Training Image segmentation Biological system modeling Computational modeling Computed tomography computer architecture Biomedical imaging Testing

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RTL Interconnect Obfuscation By Polymorphic Switch Boxes For Secure Hardware Generation

arXiv

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arXiv 2024年

作者： Chakraborty, Haimanti Vemuri, Ranga Digital Design Environments Laboratory Electrical and Computer Engineering Department University of Cincinnati CincinnatiOH United States

Logic Obfuscation is a well renowned design-for-trust solution to protect an Integrated Circuit (IC) from unauthorized use and illegal overproduction by including key-gates to lock the design. This is particularly necessary for ICs manufactured at untrusted third-party foundries getting exposed to security threats. In the past, several logic obfuscation methodologies have been proposed that are vulnerable to attacks such as the Boolean Satisfiability Attack. Many of these techniques are implemented at the gate level that may involve expensive re-synthesis cycles. In this paper, we present an interconnect obfuscation scheme at the Register-Transfer Level (RTL) using Switch Boxes (SBs) constructed of Polymorphic Transistors. A polymorphic SB can be designed using the same transistor count as its Complementary-Metal-Oxide-Semiconductor based counterpart, thereby no increased area in comparison, but serving as an advantage in having more key-bit combinations for an attacker to correctly identify and unlock each polymorphic SB. Security-aware high-level synthesis algorithms have also been presented to increase RTL interconnects to Functional Units impacting multiple outputs such that when a polymorphic SB is strategically inserted, those outputs would be corrupted upon incorrect key-bit identification. Finally, we run the SMT (Satisfiability Modulo Theories)-based RTL Logic Attack on the obfuscated design to examine its robustness. Copyright © 2024, The Authors. All rights reserved.

关键词： CMOS integrated circuits

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