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IEEE International Conference on Robotics and Automation (ICRA)

作者： M. Zinn O. Khatib B. Roth Department of Mechanical Engineering Design Division University of Stanford Stanford CA USA Department of Computer Science Robotics Laboratory University of Stanford Stanford CA USA

Many successful robotic manipulator designs have been introduced. However, there remains the challenge of designing a manipulator that possesses the inherent safety characteristics necessary for human-centered robotics. In this paper, we present a new actuation approach that has the requisite characteristics for inherent safety while maintaining the performance expected of modern designs. By drastically reducing the effective impedance of the manipulator while maintaining high frequency torque capability, we show that the competing design requirements of performance and safety can be successfully integrated into a single manipulation system.

关键词： Manipulators Safety Acceleration Impedance Torque Human robot interaction Service robots Brain injuries Robot sensing systems computer science

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Spread spectrum clock generator with delay cell array to reduce the EMI from a high-speed digital system

Spread spectrum clock generator with delay cell array to red...

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IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Jonghoon Kim Dong Gun Kam Joungho Kim Module Design Team Memory Division Device Solution Network Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Department of Electrical Engineering & Computer Science Korea Advanced Institute of Science and Technology Daejeon South Korea

ISBN: (纸本)0780384431

In high-speed digital systems, most of the EMI from the system is caused by high-speed digital clock drivers and synchronized circuits. In order to reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional spread spectrum clock generator with a phase locked loop (SSCG-PLL) has been implemented by controlling period jitter. However, the conventional SSCG-PLL becomes more difficult to implement at higher clock frequencies, in the GHz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome these problems associated with the random period jitter, we propose a spread spectrum clock generator with a delay cell array (SSCG-DCA), which controls the position of clock transitions. Measurement and simulation have demonstrated that the proposed SSCG-DCA is easier to implement and attenuating the EMI is more effective compared with the conventional SSCG-PLL. The proposed SSCG-DCA was implemented on a chip using a 0.35 /spl mu/m CMOS process and a 9 dB attenuation of the EMI was achieved at 390 MHz.

关键词： Spread spectrum communication Clocks Delay Electromagnetic interference Digital systems Jitter Phase locked loops Frequency Attenuation Driver circuits

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Twiddle-factor-based FFT algorithm with reduced memory access 16

Twiddle-factor-based FFT algorithm with reduced memory acces...

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16th International Parallel and Distributed Processing Symposium, IPDPS 2002

作者： Jiang, Yingtao Zhou, Ting Tang, Yiyan Wang, Yuke Department of Electrical and Computer Engineering University of Nevada Las Vegas Las VegasNV89119 United States ASIC Design Division Gennum Corporation KanadaON Canada Department of Computer Science University of Texas at Dallas RichardsonTX75083 United States

ISBN: (纸本)0769515738

In microprocessor-based systems, memory access is expensive due to longer latency and higher power consumption. In this paper, we present a novel FFT algorithm to reduce the frequency of memory access as well as multiplication operations. For an N-point FFT, we design the FFT with two distinct sections: (1) The first section of the FFT structure computes the butterflies involving twiddle factors WNj(j ≠ 0) through a computation/partitioning scheme similar to the Hoffman coding. In this section, all the butterflies sharing the same twiddle factor will be clustered and computed together. In this way, redundant memory access to load twiddle factors is avoided. (2) In the second section, the remaining (N - 1) butterflies involving the twiddle factor WN0are computed with a register-based breadth first tree traversal algorithm. This novel twiddle factor-based FFT is tested on the TIT MS320C62x digital signal processor. The results show that, for a 32-point FFT, the new algorithm leads to as much as 20% reduction in clock cycles and an average of 30% reduction in memory access than that of the conventional DIF FFT. © 2002 IEEE.

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Twiddle-factor-based FFT algorithm with reduced memory access

Twiddle-factor-based FFT algorithm with reduced memory acces...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Yingtao Jiang Ting Zhou Yiyan Tang Yuke Wang Department of Electrical & Computer Engineering University of Nevada Las Vegas NV USA ASIC Design Division Gennum Corporation ONT Canada Department of Computer Science University of Texas Dallas Richardson TX USA

ISBN: (纸本)0769515738

In microprocessor-based systems, memory access is expensive due to longer latency and higher power consumption. In this paper, we present a novel FFT algorithm to reduce the frequency of memory access as well as multiplication operations. For an N-point FFT, we design the FFT with two distinct sections: (1) The first section of the FFT structure computes the butterflies involving twiddle factors W N j (j ≠ 0) through a computation/partitioning scheme similar to the Hoffman coding. In this section, all the butterflies sharing the same twiddle factor will be clustered and computed together. In this way, redundant memory access to load twiddle factors is avoided. (2) In the second section, the remaining (N - 1) butterflies involving the twiddle factor W N 0 are computed with a register-based breadth first tree traversal algorithm. This novel twiddle factor-based FFT is tested on the TIT MS320C62x digital signal processor. The results show that, for a 32-point FFT, the new algorithm leads to as much as 20% reduction in clock cycles and an average of 30% reduction in memory access than that of the conventional DIF FFT.

关键词： Signal processing algorithms Discrete Fourier transforms Dairy products Signal processing Algorithm design and analysis Frequency response design engineering Application specific integrated circuits computer science Microprocessors

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The space and planetary robotics network

The space and planetary robotics network

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作者： Ellery, Alex Barnes, Dave Buckland, Rodney Welch, Chris Garry, James Zarnecki, John Gebbie, Jonathan Green, Ashley Smith, Mark Hall, David McInnes, Colin Winfield, Alan Nehmzow, Ulrich Ball, Andrew School of Engineering Kingston University London United Kingdom Dept. of Computer Science Aberystwyth University of Wales United Kingdom Dept. of Design and Innovation Open University Milton Keynes United Kingdom Space and Defence Division Logica London United Kingdom Earth Observation Navigation and Science Directorate Astrium Ltd. Stevenage United Kingdom British National Space Centre London United Kingdom Dept. of Aerospace Engineering University of Glasgow United Kingdom Intelligent Autonomous Systems Laboratory University of West of England Bristol United Kingdom Dept of Computer Science University of Essex Colchester United Kingdom Planetary and Space Sciences Research Institute Open University Milton Keynes United Kingdom

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A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier

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IEEE Journal of Solid-State Circuits 2001年第1期36卷 135-138页

作者： Po-Chiun Huang Yi-Huei Chen Chorng-Kuang Wang Circuit Design Engineering Division MediaTek Inc. Hsinchu Taiwan System-on-Chip Technology Center Industrial Technology and Research Institute Hsinchu Taiwan Department of Electrical Engineering College of Electrical Engineering and Computer Science National Taiwan University Taipei Taiwan

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum /spl plusmn/10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm/sup 2/ using 0.6-/spl mu/m digital CMOS technology.

关键词： Frequency shift keying Demodulation Limiting Detectors Signal processing Phase detection CMOS technology Integrated circuit technology Automatic control Communication system control

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Fuzzy logic control of a robot manipulator based on visual servoing

Fuzzy logic control of a robot manipulator based on visual s...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： C.S. Kim W.H. Seo S.H. Han O. Khatib Department of Mechanical Design Graduate School of Kyungnam University Masan South Korea Division of Mechanical Engineering and Automation Kyungnam University Masan South Korea Computer Science and Robotics Laboratory Department University of Stanford Stanford CA USA

ISBN: (纸本)0780370902

In this paper, a solution to a manipulation control problem (target identification and grasping) using a real platform in combination with a vision system is proposed. The task for the end-effector is to approach a randomly placed spherical object of known size. The control law is approximated by using an approach based on fuzzy logic. The controller determines the parameters of the target (a spherical object acquired from the vision system mounted on the manipulator) using a vision algorithm. The fuzzy rules are built in a supervised way, after studying the behavior of the system. Experimental results obtained using an industrial manipulator (AM1 with 6 DOF model in Samsung Electronics Co., Ltd., Korea) are presented.

关键词： Fuzzy logic Robot control Manipulators Visual servoing Control systems Machine vision Fuzzy systems Electrical equipment industry Electronics industry Industrial electronics

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Polymeric nanosphere formed from temperature-responsive polymer composed of (N,N-dimethylamino)ethyl methacrylate and ethyl acrylamide

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Journal of Polymer science 2001年第5期39卷

作者： Tae Bum Lee Kyoung Tai No Sun Hang Cho Seung Su Kim Jung Ki Seo Jin Ho Lee Soon Hong Yuk Computer Aided Molecular Design Research Center and Department of Chemistry Soong Sil University Seoul 156-743 Korea Advanced Materials Division Korea Research Institute of Chemical Technology P.O. Box 107 Yusung Taejeon 305-600 Korea Department of Polymer Science and Engineering Han Nam University 133 Ojeong Dong Daedeog Ku Taejeon 306-791 Korea

A nanosphere was formed from a temperature-responsive random copolymer of ( N , N -dimethylamino)ethyl methacrylate (DMAEMA) and ethyl acrylamide (EAAm) without a crosslinker. When the copolymerization was performed in a water/ethanol solvent mixture (90/10 v/v %) above the lower critical-solution temperature of poly(DMAEMA- co -EAAm), the nanosphere was formed with the propagation of copolymerization. Atomic force microscopy analysis and dynamic light scattering both showed the formation of nanosphere and the size was decreased as the EAAm content increased in the copolymer. To illuminate this nanosphere formation phenomena, molecular dynamic simulations were performed with model polymer solutions. According to the analysis of the simulation trajectory, the ethyl groups of ethanol bind to the hydrophobic sites of poly(DMAEMA) or poly(DMAEMA- co -EAAm), and water molecules can bind preferentially to CO groups that are abundant on the surface of the core, which is composed of oligomer and ethanol. This may enable the polymerization to proceed within the core, which is transformed into nanosphere. © 2001 John Wiley & Sons, Inc. J Polym Sci B: Polym Phys 39: 594–600, 2001

关键词： polymeric nanosphere temperature-responsive polymer molecular dynamic simulation

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A low-power cache system for embedded processors

A low-power cache system for embedded processors

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Gi-Ho Park Kil-Whan Lee Jang-Soo Lee Tack-Don Han Shin-Dug Kim Yong-Chun Kim Seh-Woong Jeong Kwang-Yup Lee Research Institute of ASIC Design Yonsei University Seoul South Korea Department of Computer Science Yonsei University Seoul South Korea MCU Team System LSI Division Samsung Electronics Company Limited Yongin si South Korea Department of Computer Engineering Seokyeong University Seoul South Korea

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor, the prototype chip of which was recently manufactured with a 0.25 /spl mu/m, 4-metal process by Samsung Electronics Co.

关键词： Cooperative caching Energy consumption Application specific integrated circuits computer science Large scale integration Embedded computing Power engineering computing design engineering Power engineering and energy Manufacturing processes

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Automated mesh generation of an arterial bifurcation based upon in vivo MR images

Automated mesh generation of an arterial bifurcation based u...

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Annual International Conference of the IEEE engineering in Medicine and Biology Society (EMBC)

作者： Seung Lee N. Piersol F. Loth P. Fischer G. Leaf B. Smith R. Yedevalli A. Yardimci N. Alperin L. Schwartz Department of Mechanical Engineering University of Illinois Chicago Chicago IL USA Mathematics and Computer Science Division Argonne National Laboratory Argonne IL USA Advanced Engineering Design Center Baxter International Round Lake IL USA Department of Radiology and Bioengineering Department University of Illinois Chicago Chicago IL USA Department of Vascular Surgery University of Chicago Chicago IL USA

ISBN: (纸本)0780364651

An automated method is described for creating a computational fluid dynamic (CFD) mesh of a blood vessel lumen geometry based on in vivo measurements taken by magnetic resonance (MR) imaging. Study of the specific geometry and flow conditions in patients with vascular disease may contribute to one's understanding of the relationship between their hemodynamic environment and conditions that lead to the development and progression of arterial disease.

关键词： Mesh generation Bifurcation Computational fluid dynamics Diseases Blood vessels Biomedical imaging Computational geometry In vivo Magnetic resonance Magnetic resonance imaging

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